Memory Controller Rewriting for Faster Multi-Level Cell Reads
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Solution Overview
Problem
The increasing use of multi-level memory cell transistors in semiconductor devices leads to deteriorated read limit performance, limiting data transfer speed despite advancements in host interface speed, and traditional methods to enhance read performance, such as increasing page size or number of dies, are costly or inefficient.
Innovation Solution
A memory system and control method that changes the writing method for recorded data to a method with fewer bits per cell and re-records the data using a smaller number of cell bits upon request, enhancing read performance without increasing cost or reducing storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level type memory cell transistors are used to increase storage capacity, then storage density is improved, but read limit performance deteriorates
Solution Approach 1:
The patent implements dynamic switching between different writing methods (SLC, MLC, TLC, QLC) based on read performance requirements. The memory controller selectively changes the writing method for recorded data when read performance degradation is detected, allowing the system to adapt between high storage density and high read performance modes as needed
Solution Approach 2:
The patent changes the parameter of 'number of cell bits' from 4 (QLC) to 2 (MLC) or 1 (SLC) by rewriting the data in the memory cells. This parameter change modifies the read performance characteristics while maintaining the same physical storage structure, enabling performance optimization without hardware reconfiguration
2Speed
If traditional methods to enhance read performance are used, then read speed is improved, but cost increases
Solution Approach 1:
Instead of using expensive static hardware solutions to improve read speed, the patent employs a dynamic software-based approach where the memory controller changes writing methods based on performance needs. This avoids the cost of manufacturing specialized high-performance memory hardware while achieving read performance improvements through intelligent data rewriting
Solution Approach 2:
The patent creates a copy of the data in the memory cells by rewriting it using a different writing method (e.g., copying QLC data back as SLC data). This copy operation enables the system to access read performance characteristics of simpler memory structures without requiring the original complex multi-level cells to be replaced
3Speed
If page size or number of dies are increased to improve read performance, then read speed is improved, but device complexity increases
Solution Approach 1:
The patent changes the parameter of 'writing method' from multi-level (QLC/TLC) to single-level (SLC/MLC) without altering the physical structure of the memory device. This parameter change improves read performance while avoiding the complexity increases that would result from increasing page size or number of dies
Solution Approach 2:
The memory controller performs the performance optimization autonomously by detecting read performance degradation and automatically changing the writing method for subsequent writes. This self-service approach improves read speed without requiring external intervention or complex system reconfiguration
Data Source
AI summary
According to one embodiment, a memory system includes an array of memory cells that store two or more bits of data each, and a memory controller to control writing data into the memory cells and reading from the memory cells. When a first command is received from a host, the memory controller reads data designated by the first command from the array and then rewrites the read data back into the array using a writing method in which a lower number of bits per memory cell is written than the originally stored manner of the read data. When a read command designating the rewritten data is received from the host, the memory controller reads from the array and transfers it to the host.