Memory Controller Routing Data to Speed-Matched NAND Chips
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Solution Overview
Problem
Existing memory systems face inefficiencies in data access and processing due to varying reading and writing speeds across different NAND chips, which can lead to suboptimal performance in data operations.
Innovation Solution
A memory system configuration that includes a controller capable of selecting NAND chips based on reading and writing speed information, optimizing data operations by directing high-access-frequency data to high-speed chips and low-access-frequency data to low-speed chips, thereby enhancing overall processing capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data operations are performed on NAND chips with varying speeds, then data access can be performed, but processing efficiency deteriorates due to suboptimal performance
Solution Approach 1:
The patent applies local quality by creating distinct data operation regions with different speed characteristics. Fast data operations are directed to high-speed NAND chips while slow data operations are directed to low-speed NAND chips. This spatial differentiation of operation speeds resolves the contradiction by allowing simultaneous optimization of both fast and slow operations in their respective regions, thereby improving overall processing efficiency without sacrificing access time for any data type.
2Productivity
If all data operations are handled uniformly across NAND chips, then system simplicity is maintained, but processing capability deteriorates due to inability to optimize for different access frequencies
Solution Approach 1:
The patent segments the data operation handling by dividing data into fast data and slow data, and by separating the processing paths for each type. The controller identifies and routes different data types to appropriate NAND chips based on their speed characteristics. This segmentation enables optimized processing capability for each data type while maintaining manageable system complexity through structured classification and routing mechanisms.
Solution Approach 2:
The patent introduces dynamic adaptability by enabling the controller to selectively switch between different data operation modes based on data characteristics. The system dynamically determines whether data should be processed as fast data or slow data and routes it accordingly to high-speed or low-speed NAND chips. This dynamic behavior allows the system to optimize processing capability for varying workloads while maintaining a relatively simple underlying hardware architecture.
Data Source
AI summary
A memory system includes a plurality of first memory chips connected to a first bus, a plurality of second memory chips connected to a second bus, and a controller that is connected to the first and second buses and configured to execute a write operation by performing processes that include selecting one of the plurality of first memory chips based on first information including data reading speed information and/or data writing speed information for the plurality of first memory chips, and selecting one of the plurality of second memory chips based on second information including data reading speed information and/or data writing speed information for the plurality of second memory chips.