Memory Controller ECC for DRAM Row Fault Correction
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Solution Overview
Problem
Dynamic random access memory (DRAM) systems face challenges in efficiently correcting errors, particularly row faults that result in uncorrectable bit errors, which can lead to data integrity issues.
Innovation Solution
A memory controller with an error correction code (ECC) engine and central processing unit (CPU) is implemented, utilizing an ECC decoder and parity check matrix to generate syndromes and correct bit errors in user data sets, including identifying row faults and correcting errors based on error information signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC decoding is used, then simple bit errors can be corrected, but row faults resulting in uncorrectable bit errors cannot be handled
Solution Approach 1:
The patent performs preliminary identification of row faults using syndrome analysis before attempting correction. By detecting row faults in advance through checking whether syndromes meet specific conditions, the system prepares correction strategies proactively, enabling it to handle uncorrectable errors that would otherwise fail conventional ECC decoding
Solution Approach 2:
The patent introduces syndrome information as an intermediary element between error detection and correction. The syndrome serves as a mediator that provides detailed error characteristics, enabling the system to distinguish between correctable bit errors and uncorrectable row faults, thus bridging the gap between simple ECC decoding and sophisticated error handling
2Productivity
If ECC decoding is performed on all errors, then processing overhead increases, but error correction efficiency improves
Solution Approach 1:
The patent applies partial action by performing syndrome-based row fault identification only when necessary, rather than applying full correction procedures to all errors. By selectively identifying row faults through syndrome checking and applying targeted correction only to identified cases, the system avoids unnecessary processing overhead while maintaining high correction efficiency
Solution Approach 2:
The patent implements feedback through syndrome analysis, where the decoding process continuously monitors error patterns and adjusts correction strategies based on syndrome conditions. This feedback mechanism enables the system to efficiently distinguish between correctable and uncorrectable errors, optimizing processing time by avoiding futile correction attempts on uncorrectable row faults
Data Source
AI summary
A memory controller controls a memory module including data chips and first and second parity chips. The memory controller includes an error correction code (ECC) engine. The ECC engine includes an ECC decoder and a memory to store a parity check matrix. The ECC decoder receives error information signals associated with the data chips, performs an ECC decoding on a codeword set from the memory module using the parity check matrix to generate a first syndrome and a second syndrome, and corrects bit errors in a user data set based on the error information signals and the second syndrome. The bit errors are generated by a row fault and uncorrectable using the first syndrome and the second syndrome. Each of the error information signals includes row fault information indicating whether the row fault occurs in at least one of memory cell rows in corresponding one of the data chips.