Memory Controller Row Hammer Mitigation via Dynamic Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge is to effectively mitigate the row hammer phenomenon in latest-generation DRAM standards like LPDDR5 or LPDDR5X without introducing new circuits, by utilizing existing functions to control access to dynamic random access memories (DRAMs).
Innovation Solution
A memory controller is configured with a rolling accumulated ACT (RAA) counter and a command scheduler. When the RAA count value exceeds a first threshold, the command scheduler extends parameters such as the issuance interval for ACT commands, the time allowing four ACT commands, or the time allowing 32 ACT commands, and recovers these values when the count falls below a second threshold.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a new standard (RFM) with RAA counter and RFM command circuit is introduced to cope with row hammer, then row hammer protection is improved, but device complexity increases
Solution Approach 1:
The memory controller utilizes its existing RAA counter and command scheduling functions to automatically detect and respond to row hammer conditions. The system monitors its own ACT command issuance patterns and autonomously adjusts timing parameters to prevent row hammer, eliminating the need for external protection circuits.
Solution Approach 2:
The existing RAA counter, originally designed for refresh management in LPDDR5/LPDDR5X standards, is repurposed to also serve row hammer protection. The command scheduler simultaneously handles both refresh commands and ACT command timing control, making the system multi-functional without adding dedicated row hammer protection hardware.
2Productivity
If ACT command issuance frequency is increased to improve memory access speed, then productivity is improved, but row hammer risk increases
Solution Approach 1:
The timing parameters (tRRD, tFAW, t32AW) are made dynamic rather than fixed. The command scheduler automatically adjusts these intervals based on real-time RAA counter values, extending them when row hammer risk is detected and reducing them when safe, allowing the system to optimize performance while preventing row hammer.
Solution Approach 2:
The system implements a feedback mechanism where the RAA counter continuously monitors ACT command issuance, and the command scheduler uses this feedback to dynamically adjust timing parameters. When the RAA count exceeds a threshold, the scheduler extends timing intervals to prevent row hammer, and when the count decreases, it restores normal timing for optimal performance.
Data Source
AI summary
A memory controller according to an embodiment of the present disclosure is configured to control an access to a dynamic random access memory (DRAM). The memory controller includes an RAA counter configured to count the number of issuance of ACT commands and a command scheduler. The command scheduler is configured, in a case where a count value of the RAA counter has become greater than a first threshold value, to change tRRD, tFAW, or t32AW to a longer value, and, in a case where the count value of the RAA counter has become smaller than a second threshold value that is smaller than the first threshold value, to recover the changed value to a value before changed.