Memory Controller Row Hammer Mitigation via OS Context Throttling
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Solution Overview
Problem
The increasing density of memory cells in memory technologies like DRAM makes them susceptible to row hammer attacks, where electrical interference causes unintended changes in non-addressed memory cells, and existing mitigation methods like increased refresh rates are inefficient and impose performance penalties.
Innovation Solution
A memory architecture that includes a memory controller capable of detecting row hammer attacks by tracking write and read frequencies, generating alerts, and mitigating them by adjusting refresh rates and involving the operating system to end, restart, or throttle execution contexts to prevent further interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are made smaller and packed closer together to achieve greater storage densities, then storage capacity is improved, but susceptibility to row hammer attacks increases due to electrical interference between tightly packed conductive paths
Solution Approach 1:
The patent segments memory addresses into aggressor rows and victim rows, allowing selective monitoring and protection. The memory controller divides memory access patterns into categories (aggressor, victim, neutral) and applies different handling strategies to each segment, enabling targeted mitigation without affecting overall memory density or performance.
Solution Approach 2:
The patent introduces an intermediary mechanism (memory controller with row hammer detection logic) that mediates between memory access requests and physical memory cells. This intermediary monitors access patterns, identifies row hammer attacks, and intervenes by adjusting refresh rates or blocking malicious accesses, thereby protecting victim rows from electrical interference without requiring physical separation of memory cells.
2Reliability
If the refresh rate for affected memory cells is increased to mitigate row hammer attacks, then memory cell stability is improved, but system performance deteriorates due to overhead
Solution Approach 1:
The patent applies local quality by differentiating refresh rates based on specific memory row characteristics. Instead of uniformly increasing refresh rates across all memory cells, the system identifies victim rows under attack and applies elevated refresh rates only to those specific rows, while maintaining normal refresh rates for other rows. This localized approach protects vulnerable cells without imposing system-wide performance penalties.
Solution Approach 2:
The patent dynamically changes the refresh rate parameter based on detected attack patterns. The memory controller monitors access frequencies and adjusts refresh rates in real-time, increasing them for victim rows during attacks and returning to normal rates when attacks cease. This dynamic parameter adjustment ensures memory stability during threats while maintaining optimal performance during normal operation.
3Reliability
If monitoring and mitigation mechanisms are added to detect and respond to row hammer attacks, then memory security is improved, but device complexity increases
Solution Approach 1:
The patent implements universal row hammer mitigation logic within the existing memory controller, allowing the same controller to handle both normal memory management tasks and row hammer detection/response. The mitigation mechanism reuses existing controller resources (address decoding, refresh control, access monitoring) for dual purposes, avoiding the need for separate dedicated hardware and minimizing additional complexity while enhancing security.
Data Source
AI summary
A method and apparatus for mitigating row hammer attacks is provided. A row hammer alert is generated by a component of a memory architecture controlling operation of a memory device. The component may be a memory controller, coherency logic, or data fabric. The component obtains a physical address of an aggressor row that caused the alert and obtains an identifier of an execution context corresponding to the physical address. The component generates an error message for a processing device, the error message including the identifier of the execution context. The processing device retrieves the error message when performing a context switch. The processing device then generates an event received by the operating system. The operating system then takes action to reduce row hammer by the execution context, such as ending, restarting, or throttling the execution context.