Memory Controller Scheduling for Row-Hammer Mitigation
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Solution Overview
Problem
As memory device integration increases, the coupling effect between adjacent word lines intensifies, leading to data damage from Row-Hammer attacks, and existing memory devices struggle to mitigate this issue effectively, especially when active commands are concentrated on specific addresses.
Innovation Solution
A memory controller is introduced with a scheduler, row-hammer detector, and memory interface to manage active commands and addresses, detecting concentrated attacks and delaying issuance to mitigate Row-Hammer effects by storing candidate addresses in an address queue and adjusting command issuance based on output control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory device increases the degree of integration to improve storage capacity, then the storage density is improved, but the coupling effect between adjacent word lines increases causing data damage from Row-Hammer attacks
Solution Approach 1:
The memory device performs preliminary detection of row-hammer attacks by monitoring active commands before data damage occurs. The detection circuit identifies when a specific word line is activated repeatedly within a predetermined time period, and preemptively prevents further activations that would cause data damage to adjacent word lines.
Solution Approach 2:
A detection circuit is introduced as an intermediary component between the command interface and the memory array. This circuit acts as a mediator that intercepts active commands, analyzes them for row-hammer patterns, and selectively blocks or allows commands based on the detected attack patterns, thereby protecting the memory cells from coupling effects.
2Difficulty of detecting and measuring
If the memory device implements counting circuits to detect row-hammer attacks, then the detection capability is improved, but the area occupied by counting circuits increases
Solution Approach 1:
The detection function is segmented and distributed across multiple memory banks rather than using a centralized counting circuit. Each bank has its own detection logic that operates independently, eliminating the need for large-area counting circuits while maintaining comprehensive row-hammer detection capability across the entire memory device.
Solution Approach 2:
Instead of using complex counting circuits, the patent uses simplified detection logic that copies the essential functionality of address monitoring. The detection circuit compares incoming active addresses with previously detected addresses in a compact manner, achieving row-hammer detection with minimal circuit area by implementing the core detection function rather than full counting capability.
Data Source
AI summary
A memory controller includes a scheduler configured to generate an active command and an active address, and determine whether to issue the active command and the active address according to an output control signal; a row-hammer detector configured to generate the output control signal by checking a row-hammer possibility based on the active command and the active address; and a memory interface configured to provide the active command and the active address issued by the scheduler to a memory device.