Memory Controller Scheduling to Reduce Buffer Row Hammering

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Solution Overview

Problem

Flash memory devices face issues with overwriting limitations and require address mapping, which leads to concentration of access on buffer memory devices, causing row hammering and potential data loss due to stress on memory cells.

Innovation Solution

A memory controller schedules processing operations based on logical address frequency, prioritizing internal management over external requests to prevent row hammering by allocating more resources and priority to internal operations when specific addresses are frequently accessed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If address mapping is implemented in flash memory devices, then data management flexibility is improved, but access concentration on buffer memory devices occurs causing row hammering

Engineering Contradiction:

Improvedata management flexibilityVSAvoiddata loss prevention

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent implements dynamic scheduling that adjusts the priority of internal management operations based on the access frequency of logical addresses. When a logical address is accessed frequently, the system dynamically increases the priority of internal management operations (such as mapping updates and garbage collection) related to that address, preventing row hammering by interleaving external access with internal maintenance tasks.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system changes the scheduling parameter (priority level) of internal management operations based on detected access patterns. By monitoring logical address access frequency and adjusting the priority parameter dynamically, the system ensures that buffer memory device stress is distributed rather than concentrated, maintaining both data management flexibility and reliability.

Inventive Principle:

Principle #35Parameter changes

2Speed

If buffer memory device is used for address mapping, then mapping speed is improved, but row hammering occurs due to concentrated access

Engineering Contradiction:

Improvemapping speedVSAvoidrow hammering stress

Core Design Contradiction:

SpeedVSObject-affected harmful factors

Solution Approach 1:

The patent performs preliminary detection of access frequency patterns before row hammering can occur. By monitoring logical address access frequency in advance and proactively adjusting the priority of internal management operations, the system prevents the harmful accumulation of stress on buffer memory device cells before data loss can occur.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The scheduling mechanism acts as an intermediary between external access requests and internal management operations. It mediates the conflict by dynamically adjusting priority levels, ensuring that buffer memory device access is distributed appropriately and row hammering is prevented while maintaining mapping speed performance.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Loss of time

If external requests are prioritized, then response time to external device is improved, but internal management operations are delayed causing performance degradation

Engineering Contradiction:

Improveexternal request response timeVSAvoidinternal management operation efficiency

Core Design Contradiction:

Loss of timeVSProductivity

Solution Approach 1:

The patent implements dynamic priority adjustment where the scheduling of internal management operations versus external requests is not fixed but adapts based on access frequency detection. This dynamic approach allows the system to optimize both external response time and internal management efficiency by adjusting priorities in real-time based on actual workload patterns.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS20250291495A1Memory controller, storage device including the same, and operating method of the memory controller

Publication Date: 2025.09.18 SK HYNIX INC

AI summary

A memory controller may store data in the nonvolatile memory device or read data from the nonvolatile memory device based on an external request; and schedule, based on appearance frequency of a logical address included in the external request, processing performance of a processing operation for the external request and an internal management operation for the nonvolatile memory device.