Memory Controller Arbiter for Same-Bank Refresh Latency
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Solution Overview
Problem
Large DRAM chips face significant latency issues during refresh operations due to the need to periodically refresh all memory cells, which increases the time required to access and write data, especially in systems with several Gigabits of storage capacity, leading to increased latency and reduced performance.
Innovation Solution
The implementation of a memory controller with an arbiter that elevates the priority of memory access requests generating row activate commands during same-bank refresh operations, allowing concurrent refresh of one bank while other banks remain accessible for read and write operations, utilizing the same-bank refresh command to reduce overhead and improve bus efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional all-bank or per-bank refresh commands are used, then all memory cells are refreshed to prevent charge leakage, but the entire memory chip becomes inaccessible during the refresh interval, causing high latency
Solution Approach 1:
The memory chip is divided into multiple independent banks, and the refresh operation is segmented to refresh only one bank at a time using same-bank refresh commands. This allows other banks to remain accessible during the refresh operation, reducing the overall refresh latency while maintaining charge retention reliability.
2Quantity of substance
If larger DRAM chip sizes are used to increase storage capacity, then more memory cells are available, but the time required to refresh all memory cells increases, further increasing latency
Solution Approach 1:
The large memory chip is organized into multiple banks that can be refreshed independently. By using same-bank refresh commands, the system can refresh one bank while simultaneously accessing other banks, thereby maintaining high storage capacity while reducing the effective refresh time experienced by the system.
Solution Approach 2:
The system maintains continuous useful action by allowing read and write operations to proceed in banks that are not currently being refreshed. This overlapping of refresh operations with normal memory operations ensures that the memory system remains productive throughout the refresh interval.
3Reliability
If refresh operations are performed frequently to maintain charge, then data integrity is preserved, but memory access performance deteriorates due to repeated access blocking
Solution Approach 1:
By segmenting the memory into multiple banks and using same-bank refresh commands, the system can perform refresh operations on one bank while maintaining full access to other banks. This segmentation allows frequent refresh operations to maintain data integrity without proportionally impacting overall memory access performance.
Solution Approach 2:
The system dynamically manages bank selection for refresh operations based on current access patterns. The arbiter dynamically prioritizes memory access requests that generate row activate commands during same-bank refresh operations, adapting the refresh schedule to maintain both data integrity and performance.
4Reliability
If the arbiter prioritizes refresh commands over memory access requests, then charge leakage is prevented, but pending read and write commands experience increased latency
Solution Approach 1:
The arbiter uses segmentation by bank to allow memory access requests to be serviced in banks that are not currently being refreshed. By prioritizing access requests that can proceed in available banks while scheduling refresh operations for other banks, the system prevents charge leakage without unnecessarily delaying pending commands.
Data Source
AI summary
A memory controller includes an arbiter. The arbiter is configured to elevate a priority of memory access requests that generate row activate commands in response to receiving a same-bank refresh request, and to send a same-bank refresh command in response to receiving the same-bank refresh request.