Memory Controller Scan Scheduling for Error Detection
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Solution Overview
Problem
The existing memory systems experience performance degradation due to unnecessary scan operations while detecting errors in memory blocks, which can delay processing and reduce overall system performance.
Innovation Solution
A memory system and operating method that selectively scan memory blocks, identifying and prioritizing 'cold' blocks for scanning, avoiding repeated scans within a scan period and incorporating sleep mode time into the scan period measurement to optimize error detection efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory controller performs periodic scan operations on all memory blocks to detect errors, then the reliability of the memory system is improved, but the productivity of the system deteriorates due to processing delays
Solution Approach 1:
The patent applies local quality by differentiating between cold memory blocks (infrequently accessed) and hot memory blocks (frequently accessed). Scan operations are performed on all blocks initially, but subsequently only on cold blocks, allowing the system to maintain reliability for error-prone areas while improving productivity by skipping frequently accessed blocks that are less likely to have undetected errors.
Solution Approach 2:
The patent implements periodic action by performing scan operations at specific intervals (scan periods) rather than continuously. The memory controller determines whether to perform a scan operation based on elapsed time since the last scan, and only performs scans on cold blocks during these periodic intervals, thereby reducing overall scan frequency while maintaining error detection capability.
2Reliability
If the memory controller performs scan operations frequently to ensure error detection, then the reliability is improved, but the loss of time increases due to repeated scanning
Solution Approach 1:
The patent reduces time loss by applying local quality differentiation between cold and hot memory blocks. Scan operations are concentrated on cold blocks that require monitoring, while hot blocks are excluded from repeated scanning. This selective approach maintains error detection stability for vulnerable blocks while minimizing the total time consumed by scan operations across the entire memory system.
Solution Approach 2:
The patent applies partial action by performing scan operations on only a subset of memory blocks (cold blocks) rather than all blocks. This partial scanning approach is sufficient to maintain reliability for the most error-prone areas while significantly reducing the time loss associated with comprehensive scanning of the entire memory space.
3Measurement precision
If the memory controller scans all memory blocks uniformly, then the measurement precision of error detection is maintained, but the device complexity increases due to management overhead
Solution Approach 1:
The patent manages device complexity by implementing local quality tracking through maintaind a scan management data structure that records the cold/hot status of each memory block. This organized approach allows the controller to make informed decisions about which blocks to scan, maintaining measurement precision for error detection while reducing the complexity of scan management compared to uniform scanning of all blocks.
Solution Approach 2:
The patent applies segmentation by dividing memory blocks into distinct categories (cold blocks and hot blocks) based on access patterns. This segmentation is reflected in the scan management data structure that tracks individual block statuses. By segmenting the scanning task into targeted operations on cold blocks versus excluded hot blocks, the system maintains detection accuracy while simplifying the overall scan management process.
Data Source
AI summary
Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may completely scan each of one or more target memory blocks among the plurality of memory blocks, once in each scan period to detect an error in data stored in the corresponding target memory block and may block an attempted second scan of each target memory block in a scan period in which the corresponding target memory block has already been scanned until the scan period is completed.