Memory Controller Scheduling for DRAM Bandwidth Utilization
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Solution Overview
Problem
Current memory access methods for DRAM are limited by inherent parameters such as tRRD and tFAW, leading to reduced bandwidth utilization and the 'small cell N+1' problem, where cells need to be enlarged to accommodate higher frequencies, resulting in decreased memory utilization and increased idle periods.
Innovation Solution
A memory scheduling method that utilizes idle periods between commands to access different ranks of memory, decoupling ACT commands from operation commands and allowing flexible scheduling, thereby improving bandwidth utilization without enlarging cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple Banks are used to duplicate a lookup table and consecutively access multiple Banks, then the tRC parameter is avoided and bandwidth utilization is improved, but the tRRD and tFAW parameters cause additional idle periods and reduce overall efficiency
Solution Approach 1:
The memory system is divided into multiple Ranks (Rank0 and Rank1), each containing multiple Banks. This segmentation allows independent access to different Ranks, enabling the controller to switch between Ranks during idle periods caused by tRC, tRRD, or tFAW constraints within a single Rank, thereby reducing overall idle time and improving bandwidth utilization.
Solution Approach 2:
The invention maintains continuous useful action by utilizing idle periods for alternative productive operations. When one Rank is constrained by tRC, tRRD, or tFAW parameters, the controller immediately switches to accessing the other Rank, ensuring the bus remains productive and eliminating idle periods through continuous useful memory operations.
2Speed
If the working frequency of DRAM is increased to improve performance, then higher speed is achieved, but the tWTR and CL parameters increase, causing lower bandwidth utilization and more idle periods
Solution Approach 1:
The invention implements periodic action through interleaved access patterns between Rank0 and Rank1. By alternately accessing commands for different Ranks in a periodic manner, the system can accommodate increased tWTR and CL values at higher frequencies while maintaining high bandwidth utilization, as the periodic switching allows each Rank to complete its operations without excessive idle time.
Solution Approach 2:
The controller prepares and queues commands for both Rank0 and Rank1 in advance, allowing it to immediately switch to a pre-prepared command for the other Rank when idle periods occur. This preliminary preparation of alternative commands ensures that higher frequencies with increased tWTR and CL do not result in bandwidth loss.
3Speed
If the size of each Cell is increased to accommodate higher frequencies and meet tRRD and tFAW parameters, then frequency requirements are met, but memory utilization decreases due to the small cell N+1 problem
Solution Approach 1:
The invention adds the Rank dimension to the traditional Bank hierarchy, creating a four-level memory organization (Rank-Bank-Row-Column). This dimensional expansion allows the system to meet high frequency requirements through architectural diversity rather than increasing cell size, thereby avoiding the small cell N+1 problem and maintaining high memory utilization while achieving DDR3-2133 and higher frequencies.
Data Source
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AI summary
The present invention discloses a memory scheduling method, which mainly includes: writing a command into a second memory in a periodic interval for writing, by a memory controller, a command into a first memory. Through the method in the present invention, a row strobe command and a corresponding operation command can be flexibly invoked, thereby improving bandwidth utilization of a memory. An embodiment of the present invention further provides a corresponding memory controller. The present invention breaks through a limitation that an ACT and a corresponding operation command need to be consecutively written, and improves table lookup and packet buffer efficiency.