Memory Controller Scheduling for Data Bus Utilization
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Solution Overview
Problem
The LP5 memory standard presents challenges in achieving maximum utilization of the data bus while efficiently scheduling memory commands, due to requirements such as two activate commands per bank, sync commands, and constraints on data transmission beats.
Innovation Solution
A scheduling paradigm is proposed where clock cycles are divided into alternating sets for transmiting activate commands and other commands, with specific timing delays for read/write commands to achieve a '2-6' or '6-2' cadence, maximizing data bus utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory commands are scheduled according to LP5 standard requirements (two activate commands per bank, sync commands, constrained data transmission beats), then memory operation reliability is ensured, but data bus utilization is reduced due to idle clock cycles and transmission gaps
Solution Approach 1:
The patent segments the data bus transmission into multiple beats (first beat and second beat) with intermediate idle cycles, and further segments memory operations into different banks (first bank, second bank, etc.). By interleaving data transmission from different banks in different beats, the system maintains LP5 standard compliance while reducing overall idle time and improving data bus utilization.
Solution Approach 2:
The patent implements periodic data transmission patterns where data from different banks is transmitted in an alternating periodic fashion across multiple beats. This periodic interleaving allows the data bus to remain active more consistently while still respecting the timing constraints of the LP5 standard, thereby improving utilization without sacrificing reliability.
2Stability of the object's composition
If data transmission is constrained to two beats per bank access with required idle cycles between beats, then memory device stability is maintained, but bandwidth efficiency is reduced due to unused clock cycles
Solution Approach 1:
The patent achieves continuity of useful action by interleaving data transmission from multiple banks across different beats. While individual bank transmissions still follow the two-beat pattern with idle cycles, the overall system maintains continuous data bus utilization by switching between banks, effectively eliminating wasted bandwidth and improving efficiency without compromising device stability.
Solution Approach 2:
The patent introduces a new dimension of bank selection to the data transmission process. Instead of transmitting all data sequentially from a single bank, the system adds the dimension of bank interleaving, allowing data from multiple banks to be transmitted in parallel across different beats. This dimensional expansion allows the system to maintain stability constraints while improving bandwidth efficiency.
3Device complexity
If alternating clock cycles are used for activate commands and other commands, then command scheduling complexity is reduced, but data bus utilization may be compromised due to command transmission taking precedence
Solution Approach 1:
The patent segments clock cycles into distinct types (first clock cycles for activate commands, second clock cycles for other commands) and segments data transmission into different beats. This segmentation allows the scheduler to follow a simple alternating pattern while still achieving high data bus utilization through intelligent interleaving of data from multiple banks across the segmented beats.
Solution Approach 2:
The patent makes the clock cycle structure universal by establishing a repeating pattern that can accommodate both activate commands and other commands in a systematic way. This universal alternating pattern simplifies scheduling while the multi-beat data transmission structure provides the flexibility needed to maintain high data bus utilization across different command types.
Data Source
AI summary
Techniques for scheduling memory operations are disclosed in which alternate read/write commands within a multi-bank memory operation are delayed beyond a minimum timing parameter in order to increase memory data bus utilization. The remaining read/write commands are not delayed beyond the minimum timing parameter. Every other clock cycle (e.g., even clock cycles) within the memory operation is reserved for activate commands, while other commands such as sync and read/write are scheduled on the intervening clock cycles (e.g., odd clock cycles). For memory devices for which a sync command (which causes a clock of the memory data bus to start) is to precede a corresponding read/write command by a number of clock cycles that would place it in a cycle reserved for activate commands, a particular operation mode is disclosed in which the memory device internally delays a received sync command.