Memory Controller Scheduling for Non-Uniform Latency Channels
Solution Overview
Problem
Computing systems face challenges in maintaining high performance due to differences in access latencies between various memory types, leading to inefficiencies in data access and potential data collisions on shared memory buses.
Innovation Solution
A memory controller with a scheduler that translates memory requests into commands, determines suitable issuance times to avoid data collisions by considering access latencies and using arbitration logic to select commands based on priority, age, and other criteria, ensuring that response data from different memory types arrives in an orderly fashion on the shared memory data bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory types with different access latencies are integrated on the same channel, then memory capacity and performance are improved, but data collisions and out-of-order arrivals occur
Solution Approach 1:
The patent applies preliminary action by having the memory controller predict future data arrival times based on known access latencies of different memory types. The controller proactively schedules memory requests to account for these predicted arrival times, preventing out-of-order arrivals before they occur. This is implemented through a scheduling mechanism that uses latency information to determine optimal issue timing for each memory request.
2Speed
If memory requests are issued without considering access latencies, then processing speed is improved, but data collisions on shared bus occur
Solution Approach 1:
The system performs preliminary scheduling of memory requests by predicting when data will be available based on access latency characteristics. This allows the memory controller to issue requests at optimal times without causing bus collisions, maintaining high speed while avoiding conflicts. The scheduling logic proactively determines safe issue times before actual data transfer begins.
3Reliability
If access latencies are considered in scheduling, then data collision prevention is improved, but scheduling complexity increases
Solution Approach 1:
The patent changes the parameter approach by using fixed, known access latency values for different memory types rather than dynamic measurements. This allows the scheduling mechanism to use simple lookup tables or predefined latency profiles, reducing computational complexity while maintaining reliable collision prevention. The system transforms a potentially complex real-time calculation problem into a simpler parameter-based scheduling approach.
Data Source
AI summary
Systems, apparatuses, and methods for identifying response data arriving out-of-order from two different memory types are disclosed. A computing system includes one or more clients for processing applications. A memory channel transfers memory traffic between a memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a given point in time when read data is to be scheduled to arrive on the memory bus from memory. The memory controller associates a unique identifier with the given point in time. The memory controller identifies a given command associated with the arriving read data based on the given point in time.