Memory Controller Scoreboard for Partial Data Processing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing memory systems experience delays in operational performance due to the sequential loading of data from a main memory area to an application memory area, which hinders efficient data processing and usage.

Innovation Solution

A memory system with a scoreboard mechanism that allows processing of data in units of macro operations, enabling the memory controller to utilize sub-data from the application memory area before all sub-data is fully transferred, by using a first memory area for the operating system and a second memory area for applications, and employing a register set to track data progression and completion status.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is sequentially loaded from the first memory area to the second memory area, then data transfer completeness is ensured, but operational delay increases

Engineering Contradiction:
Improvedata transfer completenessVSAvoidoperational delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The scoreboard mechanism performs preliminary tracking of data transfer status before the entire transfer is complete. By maintaining full/empty bits that indicate the availability of sub-data in advance, the system enables the processor to begin operations on available data portions without waiting for the complete data set, thus reducing operational delay while ensuring transfer completeness through continuous status monitoring.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The scoreboard provides continuous feedback through full/empty bits that indicate the transfer status of each sub-data portion. This feedback mechanism allows the memory controller to dynamically determine which data portions are ready for processing and which are still being transferred, enabling optimized concurrent operations that reduce overall operational delay while maintaining data integrity.

Inventive Principle:
Principle #23Feedback

2Reliability

If data processing waits for complete data transfer, then data integrity is maintained, but processing speed decreases

Engineering Contradiction:
Improvedata integrityVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The data transfer and processing operations are segmented into sub-data portions, each tracked by individual full/empty bits in the scoreboard. This segmentation allows the processor to operate on completed sub-data portions independently while other portions are still being transferred, thereby maintaining data integrity for each segment while significantly improving overall processing speed through parallel execution.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs partial processing actions on the data that has been transferred so far, rather than waiting for the complete data set. By processing available sub-data portions immediately when their full/empty bits indicate readiness, the system achieves faster throughput while maintaining integrity through the scoreboard's continuous status verification.

Inventive Principle:
Principle #16Partial or excessive action

3Productivity

If the memory system processes data in units of macro operations, then operational efficiency improves, but system complexity increases

Engineering Contradiction:
Improveoperational efficiencyVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The scoreboard is designed as a universal tracking mechanism that handles multiple data transfer operations simultaneously using a standardized set of full/empty bits for each sub-data portion. This multi-functional scoreboard structure enables the system to process various macro operations efficiently without requiring separate tracking mechanisms for each operation type, thus improving operational efficiency while controlling system complexity through reuse of the same structural elements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9575759B2Memory system and electronic device including memory system
Publication Date: 2017.02.21 SAMSUNG ELECTRONICS CO LTD
  • US9575759B2 patent drawing
  • US9575759B2 patent drawing
  • US9575759B2 patent drawing

AI summary

A memory system processing data according to a received first request may include a main memory and a memory controller. The main memory may comprise a first area and a second area, and may be configured to provide data from the first area to the second area. The memory controller may comprise a scoreboard configured to indicate that a first piece of sub-data of a first set of sub-data of the data has been provided from the first area to the second area. Based on the scoreboard, the memory controller may be configured to perform processing of the first request by using the first piece of sub-data before providing of other pieces of sub-data of the first set of sub-data from the first area to the second area is completed.