Memory Controller Second Core Parallel Initialization

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Solution Overview

Problem

The increasing working frequency of memory chips leads to prolonged memory initialization durations due to the need for higher time sequence precision, resulting in longer computer startup times.

Innovation Solution

Incorporating a second processor core within the memory controller to perform memory initialization tasks, reducing control information transmission delays and allowing parallel processing with the primary processor core, thereby shortening memory initialization time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If memory chip working frequency is increased to improve data transmission speed, then memory initialization duration is prolonged due to higher time sequence precision requirements

Engineering Contradiction:

Improvedata transmission speedVSAvoidmemory initialization duration

Core Design Contradiction:

SpeedVSDuration of action of moving object

Solution Approach 1:

The invention divides the memory initialization process into two independent segments: a first processor core handles initialization configuration and system configuration, while a second processor core specifically handles memory training. This segmentation allows parallel execution of initialization tasks, reducing the total initialization duration despite high memory chip working frequencies that require extensive memory training for time sequence precision.

Inventive Principle:

Principle #1Segmentation

2Device complexity

If a single processor core performs all memory initialization tasks sequentially, then device complexity is reduced, but memory initialization duration is excessively long

Engineering Contradiction:

Improveprocessor structure complexityVSAvoidmemory initialization duration

Core Design Contradiction:

Device complexityVSDuration of action of moving object

Solution Approach 1:

The invention transitions from a single-processor-dimension approach to a multi-processor-core dimension, enabling parallel execution of memory initialization tasks. The first processor core and second processor core operate simultaneously on different aspects of initialization, fundamentally changing the time dimension of the initialization process from sequential to concurrent execution.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Reliability

If the processor core continuously adjusts parameters during memory training to meet time sequence precision requirements, then memory chip reliability is improved, but memory initialization duration is greatly increased

Engineering Contradiction:

Improvememory chip reliabilityVSAvoidmemory initialization duration

Core Design Contradiction:

ReliabilityVSDuration of action of moving object

Solution Approach 1:

The second processor core is dedicated specifically to memory training tasks, allowing it to self-focus on achieving time sequence precision without being interrupted by other initialization configuration tasks. This dedicated assignment enables the memory training process to complete more efficiently while maintaining the necessary reliability adjustments for high-frequency memory chips.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS12254200B2Memory initialization apparatus and method, and computer system

Publication Date: 2025.03.18 HUAWEI TECH CO LTD

AI summary

A memory initialization apparatus and method, and a computer system are provided. The memory initialization apparatus includes a first processor core and a memory controller that includes at least one second processor core. In a memory initialization process, the first processor core may invoke the second processor core to perform memory initialization. This helps to shorten memory initialization duration.