Memory Controller Segmentation for Data Accuracy

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Solution Overview

Problem

Existing memory systems face challenges in accurately storing and retrieving data due to threshold voltage fluctuations in cell transistors, leading to potential errors in data storage and retrieval, especially when writing data to multiple cell units sharing a word line.

Innovation Solution

The memory system employs a controller that instructs the memory device to write data to multiple cell transistors while monitoring and correcting errors, using error correction codes and verify voltages to ensure accurate data storage and retrieval by identifying and managing threshold voltage states in cell transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If data is written to multiple cell units sharing a word line, then storage capacity is improved, but threshold voltage fluctuations cause data accuracy to deteriorate

Engineering Contradiction:
Improvestorage capacityVSAvoiddata accuracy
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The controller performs preliminary actions by storing write data in a buffer before writing to cell units, and by sequentially writing data to different cell units while maintaining the buffer. This allows the system to prepare data in advance and manage write operations in a controlled sequence, preventing simultaneous writes that would cause threshold voltage fluctuations and data errors.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system segments the writing process by dividing data into separate write operations for different cell units. Instead of writing to all cell units simultaneously, the controller writes to one cell unit at a time from the buffer, isolating the write operations in time and preventing interference between adjacent cell units sharing the same word line.

Inventive Principle:
Principle #1Segmentation

2Reliability

If sequential write operations are performed to avoid write disturbances, then data accuracy is improved, but writing time is increased

Engineering Contradiction:
Improvedata accuracyVSAvoidwriting time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The controller performs preliminary action by pre-storing write data in a buffer before initiating sequential writes to cell units. This buffer preparation allows the controller to efficiently manage the sequential write process without waiting for data preparation during the write operations, thereby reducing overall writing time while maintaining data accuracy through sequential operations.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If error correction codes are used to correct threshold voltage errors, then data reliability is improved, but device complexity is increased

Engineering Contradiction:
Improvedata reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system implements feedback by using verify operations after writing to check the threshold voltage states of cell transistors. The controller compares the actual stored data with the expected data and uses this feedback information to detect and correct errors, adjusting subsequent write operations accordingly. This feedback mechanism improves data reliability while keeping the complexity manageable by using simple comparison and correction procedures.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10431322B1Memory system
Publication Date: 2019.10.01 KIOXIA CORP
  • US10431322B1 patent drawing
  • US10431322B1 patent drawing
  • US10431322B1 patent drawing

AI summary

According to one embodiment, a first string is coupled to the bit line via a first transistor and includes a first cell transistor. A second string is coupled to the bit line via a second transistor and includes a second cell transistor. The first and second cell transistors are coupled to the word line. A controller is configured to instruct the memory device to write first data to the first cell transistor and to write second data to the second cell transistor. The controller is further configured to instruct the memory device to read data from the first cell transistor while storing the first data and the second data after making the instruction for writing the first data and the second data.