Non-volatile Memory Controller Segmentation for Parallel Data Access
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Solution Overview
Problem
Conventional non-volatile memory devices, such as flash memory, suffer from slow data access speed and data loss or damage issues due to their inability to efficiently manage and recover data across multiple memory blocks.
Innovation Solution
A non-volatile memory device architecture that includes a main controller and multiple sub-controllers and memory blocks, where data is divided into sub-data and saved across multiple blocks with backup copies, allowing for increased data access speed and error tolerance through multiplexing and independent operation of sub-controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is saved in a single memory block without division, then device complexity is low, but data access speed is slow
Solution Approach 1:
The patent divides the memory system into multiple independent memory blocks (first memory block, second memory block, third memory block) each with its own sub-controller. The main controller segments data into multiple sub-data portions and distributes them across different memory blocks simultaneously, enabling parallel access and significantly improving data access speed while maintaining manageable device complexity through modular architecture
2Productivity
If data is divided and saved across multiple memory blocks, then data access speed increases, but device complexity increases
Solution Approach 1:
The system segments both data and control functions: data is divided into sub-data portions stored in different memory blocks, and control is divided between a main controller and multiple sub-controllers. This segmentation enables parallel data processing operations that improve productivity while the hierarchical control structure keeps device complexity manageable
Solution Approach 2:
The patent implements dynamic task distribution where the main controller can dynamically assign different operations (read, write, erase) to different sub-controllers and memory blocks based on current processing needs. This dynamic allocation optimizes data processing speed by utilizing all memory blocks simultaneously for different operations, improving overall system productivity without requiring permanent complex interconnections
3Reliability
If no backup data is saved, then device complexity is low, but data reliability is poor when data loss occurs
Solution Approach 1:
The patent implements a backup mechanism where critical data is copied and stored in multiple memory blocks. When data is written to the first memory block, a backup is simultaneously created in the second or third memory block. This copying approach ensures data reliability through redundancy while maintaining relatively low device complexity by using simple duplicate storage rather than complex error correction codes
Solution Approach 2:
The system prepares backup storage spaces in advance within the memory architecture. Before data loss can occur, backup copies are already positioned in alternative memory blocks, providing immediate protection against data loss without requiring complex real-time detection and recovery mechanisms, thus achieving high reliability with minimal added complexity
4Reliability
If backup data is saved in multiple memory blocks, then data loss prevention is improved, but device complexity increases
Solution Approach 1:
The patent uses simple data copying to create backup portions in different memory blocks. When data is stored in the first memory block, identical copies are created and stored in the second and/or third memory blocks. This copying strategy achieves high error tolerance and reliability by ensuring data survival even if one block fails, while keeping device complexity low through the simplicity of the copy operation and straightforward backup management
Data Source
AI summary
A non-volatile memory device, a data access circuit and a data access method are provided. The non-volatile memory device includes a main controller, a plurality of sub-controllers and a plurality of memory blocks. The sub-controllers are coupled to the main controller and are used to execute the tasks assigned by the main controller. The memory blocks are respectively coupled to the corresponding sub-controllers. The main controller is used to divide a received main data into a plurality of sub-data, and the sub-data are respectively saved in the memory blocks through corresponding sub-controllers. Therefore, the data access speed of the non-volatile memory device is substantially speeded-up.