Memory Controller Segmentation for Write Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In memory systems with NAND type flash memory, there is a need for efficient data management and storage strategies that balance storage capacity and latency between different nonvolatile memory types, particularly when handling varying data sizes and ensuring high efficiency in write operations.
Innovation Solution
A memory system comprising first and second nonvolatile memory, with a controller that determines storage destinations based on data size, using NAND type flash memory for larger data sets and MRAM or other fast nonvolatile memory for smaller data, allowing for efficient data management through logical and physical address translation and cache management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is stored in nonvolatile cache memory (second nonvolatile memory), then write latency is reduced, but storage capacity is limited
Solution Approach 1:
The storage system is segmented into two distinct nonvolatile memory types: fast nonvolatile cache memory (second nonvolatile memory) for small, frequent writes, and large-capacity nonvolatile memory (first nonvolatile memory) for bulk storage. The controller segments write operations based on data size thresholds, directing small writes to the cache memory for low latency and large writes to the capacity-optimized memory, thereby resolving the contradiction between speed and storage capacity.
2Quantity of substance
If data is stored in large-capacity nonvolatile memory, then storage capacity is increased, but write latency increases
Solution Approach 1:
Different storage locations are assigned different quality characteristics: the second nonvolatile memory provides high-speed local storage for small data sets that require frequent access, while the first nonvolatile memory provides high-capacity storage for larger data sets. The controller applies local quality by selecting the appropriate storage location based on data size, ensuring that each data write operation benefits from the optimal latency characteristics of its designated storage medium.
3Measurement precision
If the controller waits to execute matching between management information before transmitting response, then data management accuracy is improved, but response time to host increases
Solution Approach 1:
The controller performs preliminary actions by generating management information (L2P table updates, cache tag updates) in advance and preparing the mapping data structures before the matching operation is fully required. The response to the host is transmitted based on preliminary determination of the storage destination, while the actual matching and validation of management information proceeds in the background, thereby reducing the host-perceived response time while maintaining data management accuracy.
4Reliability
If the controller stores data in both first and second nonvolatile memory, then data redundancy is increased, but write operations become more complex
Solution Approach 1:
The controller uses parameter changes, specifically data size thresholds and memory type characteristics, to determine the storage destination. By changing the parameter of data size classification, the system simplifies the write operation decision process: small writes go to the second nonvolatile memory, large writes go to the first nonvolatile memory. This parameter-based routing reduces write operation complexity while maintaining appropriate data redundancy through the dual-memory architecture.
Data Source
AI summary
According to one embodiment, a controller transmits a response to a write request to a host before executing matching between first management information and second management information.