Memory Controller Segmentation for Write Performance

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Solution Overview

Problem

Memory systems face performance degradation and increased lifespan reduction when operating in force unit access mode, and are prone to data write failures due to sudden power loss.

Innovation Solution

Implementing a memory system with a memory controller that differentiates between two types of memory blocks for data storage, where the first block operates faster but has less capacity and the second block has more capacity but slower operation, and using a volatile buffer to temporarily store data before writing it to these blocks, while also employing an auxiliary power unit to manage power loss scenarios.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is written to a single memory block with high operation speed, then write performance is improved, but storage capacity is reduced

Engineering Contradiction:
Improvewrite performanceVSAvoidstorage capacity
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The memory device is divided into multiple memory blocks (first memory block and second memory block) with different characteristics. The first memory block is optimized for fast write operations while the second memory block provides additional storage capacity, allowing the system to segment write operations between blocks to achieve both high performance and adequate capacity.

Inventive Principle:
Principle #1Segmentation

2Reliability

If data is written directly to the memory device in force unit access mode, then data integrity is ensured, but write performance deteriorates

Engineering Contradiction:
Improvedata integrityVSAvoidwrite performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

A buffer is introduced as an intermediary component between the host and the memory device. The buffer temporarily stores write data before it is transferred to the memory device, allowing the host to receive immediate acknowledgment while the data is asynchronously written to memory blocks, thus maintaining both data integrity and write performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If a single memory block is used for data storage, then device complexity is reduced, but write performance and lifespan are degraded

Engineering Contradiction:
Improvememory block configurationVSAvoidwrite performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

Different memory blocks are assigned different local qualities or characteristics. The first memory block is configured for fast write operations with optimized parameters, while the second memory block provides supplementary storage. This local differentiation allows each block to excel at its specific function, improving overall write performance without excessive complexity.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11614886B2Memory system and operating method thereof
Publication Date: 2023.03.28 MIMIRIP LLC
  • US11614886B2 patent drawing
  • US11614886B2 patent drawing
  • US11614886B2 patent drawing

AI summary

A memory system may write, when operating in a force unit access mode, first write data requested by the host to a buffer for temporarily storing data to be written the memory device and a first memory block among the plurality of memory blocks, and may write, when the size of the data accumulatively stored in the buffer is greater than or equal to A which is a unit of a size in which data is written to a second memory block among the plurality of memory blocks, second write data of size A among the data stored in the buffer to the second memory block. The operation speed of the first memory block may be set faster than the operation speed of the second memory block and the storage capacity of the first memory block may be set smaller than the storage capacity of the second memory block.