Memory Controller Selective Rank Access
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Solution Overview
Problem
As signaling rates in DRAMs increase, the extended data burst length leads to retrieval and transmission of unneeded data, wasting power and causing thermal loading, while also throwing the command/address and data path resources out of balance, preventing back-to-back memory access commands.
Innovation Solution
Implementing a memory system with independently accessible memory sub-ranks via separate chip-select lines or alternative techniques like staggered command/address sampling and chip-select assertion polarities, allowing for concurrent, time-interleaved memory access operations with reduced data granularity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data burst length is extended to meet peak data transfer rates, then bandwidth is improved, but power consumption increases and thermal loading increases
Solution Approach 1:
The memory device is divided into multiple ranks (first rank and second rank) that can be independently accessed. Each rank has its own chip-select line and data lines, allowing selective access to individual ranks based on memory access patterns. This segmentation enables the system to retrieve only the necessary data from specific ranks rather than loading entire extended bursts from all ranks, thereby reducing power consumption while maintaining peak data transfer rates when needed.
2Speed
If data burst length is extended to meet peak data transfer rates, then bandwidth is improved, but thermal loading increases
Solution Approach 1:
The memory device is divided into multiple ranks (first rank and second rank) that can be independently accessed. Each rank has its own chip-select line and data lines, allowing selective access to individual ranks based on memory access patterns. This segmentation enables the system to retrieve only the necessary data from specific ranks rather than loading entire extended bursts from all ranks, thereby reducing power consumption while maintaining peak data transfer rates when needed.
3Productivity
If data burst length is extended, then data output is improved, but command/address and data path resources are thrown out of balance
Solution Approach 1:
The memory device is divided into multiple ranks (first rank and second rank) that can be independently accessed. Each rank has its own chip-select line and data lines, allowing selective access to individual ranks based on memory access patterns. This segmentation enables the system to retrieve only the necessary data from specific ranks rather than loading entire extended bursts from all ranks, thereby reducing power consumption while maintaining peak data transfer rates when needed.
Solution Approach 2:
The memory controller dynamically selects which rank(s) to access based on the memory access command. The controller can independently activate the first rank, the second rank, or both ranks simultaneously by asserting appropriate chip-select signals. This dynamic control allows the system to adaptively balance data output requirements with command/address and data path resource utilization, preventing resource imbalance during extended burst operations.
4Productivity
If data burst length is extended, then data output is improved, but memory access commands cannot be transmitted back-to-back
Solution Approach 1:
The memory device is divided into multiple ranks (first rank and second rank) that can be independently accessed. Each rank has its own chip-select line and data lines, allowing selective access to individual ranks based on memory access patterns. This segmentation enables the system to retrieve only the necessary data from specific ranks rather than loading entire extended bursts from all ranks, thereby reducing power consumption while maintaining peak data transfer rates when needed.
Solution Approach 2:
The memory controller can initiate memory access commands to different ranks in advance and overlap their execution. By using multiple independent ranks with separate chip-select lines, the controller can pipeline memory operations where one rank is being accessed while another rank is being prepared for the next access. This preliminary action and overlapping of operations enables memory commands to be transmitted back-to-back without waiting for extended burst completions, reducing access latency.
Data Source
AI summary
A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.