Memory Controller Selective Erase Testing

The patent applies partial action by performing test operations selectively rather than after every erase operation. Test operations are conducted only when error memory cells are detected during a erase operation, or after a predetermined number of erase operations. This partial testing approach maintains reliability by catching actual errors while avoiding the productivity loss of universal testing after each erase.

The patent changes the parameter of test operation frequency from a fixed value (after every erase) to a variable value based on error detection results. When error memory cells are detected, test operations are performed; when no errors are detected, test operations are skipped. This dynamic parameter adjustment resolves the contradiction by adapting reliability checking to actual memory block conditions.

The patent performs test operations partially - only when error memory cells are detected during erase operations or after predetermined numbers of erases. This selective approach maintains measurement precision for detecting actual errors while avoiding unnecessary time consumption from redundant test operations on healthy memory blocks.

The patent implements skipping of test operations when error memory cells are not detected during erase operations. By rushing through the erase operation without subsequent testing when conditions permit, the system recovers time while maintaining the capability to perform thorough testing when errors are detected, thus balancing measurement precision with time efficiency.