Memory Controller Self-Test Reporting with Extended Protocol Headers

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Solution Overview

Problem

Existing storage systems lack efficient mechanisms for performing self-test operations in memory devices, which are crucial for ensuring data integrity and device health, and there is a need for improved communication protocols to facilitate these tests.

Innovation Solution

A memory controller and storage device system that includes a host interface to receive diagnostic commands for self-test operations and generates responses with additional header segments containing test results, using Protocol Information Units (PIUs) to enhance communication and reporting.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If traditional protocol information units are used for self-test operations, then communication between host and memory controller is maintained, but detailed test result information cannot be efficiently transmitted

Engineering Contradiction:
Improvetest result informationVSAvoidcommunication protocol structure
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

The protocol information unit is segmented into distinct fields: a basic header segment for standard communication and an extra header segment specifically for carrying self-test operation result information. This segmentation allows detailed test results to be transmitted without disrupting the existing communication protocol structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The self-test result information is extracted from the standard protocol framework and placed into a dedicated extra header segment. This extraction enables specialized data transmission while maintaining compatibility with the basic protocol structure, solving the problem of transmitting detailed test results without overhauling the entire communication system.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If self-test operations are implemented in memory devices, then data integrity and device health can be monitored, but additional communication overhead and processing complexity are introduced

Engineering Contradiction:
Improvedata integrityVSAvoidcommunication protocol
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The protocol information unit structure is designed to serve multiple functions: standard data transmission through the basic header segment and self-test result communication through the extra header segment. This multi-functionality allows the same communication framework to handle both regular operations and diagnostic functions without requiring separate protocols.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The memory controller performs self-test operations and generates result information that is then transmitted back to the host using the same communication interface. This self-service capability allows the device to monitor its own health status without requiring external testing equipment, improving reliability while keeping the added complexity manageable through protocol extension.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12406744B2Memory controller, storage device, and operating method of storage device
Publication Date: 2025.09.02 SK HYNIX INC
  • US12406744B2 patent drawing
  • US12406744B2 patent drawing
  • US12406744B2 patent drawing

AI summary

A memory controller performs a self-test operation on a memory device in response to a diagnostic command received from a host. The controller includes a host interface that receives the diagnostic command and a processor that executes the self-test and generates a corresponding response. The response transmitted to the host includes a basic header segment used in standard protocol communication and an extra header segment that carries result information indicating the outcome of the self-test. This structure enables efficient diagnostic communication between the host and the memory controller without disrupting regular memory operations.