Memory Controller with Separate Write and Read Caches
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Solution Overview
Problem
Memory controllers face challenges in managing data coherence and reducing latency and energy consumption due to data hazards and bottlenecks at the interface between the system and memory, particularly when dealing with different memory types and reordering of data accesses.
Innovation Solution
A memory controller design featuring separate write and read data caches with coherency circuitry to manage data coherence, allowing for reordering of access requests and reducing bottlenecks, while buffering write requests to minimize latency and energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If write responses are returned before writes are made (with write buffering), then throughput is improved, but data hazards and coherency management complexity increase
Solution Approach 1:
The patent divides the cache into separate write data cache and read data cache structures. Write requests are handled by the write data cache which can buffer and merge writes, while read requests are handled by the read data cache. This segmentation allows independent optimization of write and read operations, enabling write buffering for improved throughput while managing coherency through dedicated coherency circuitry that tracks dependencies between the two caches.
Solution Approach 2:
The patent introduces coherency circuitry as an intermediary component that manages data coherency between the write data cache and read data cache. This coherency circuitry acts as a mediator that tracks write dependencies, manages buffer status, and ensures proper ordering of memory operations, thereby enabling write buffering without requiring complex hazard detection logic throughout the entire system.
2Productivity
If access requests are reordered to improve throughput, then productivity increases, but data hazards such as read-after-write hazards are introduced
Solution Approach 1:
The patent employs coherency circuitry that performs preliminary tracking of write dependencies and buffer status before executing memory operations. The coherency circuitry maintains information about pending writes and their dependencies, allowing the system to proactively manage reordering decisions and prevent data hazards before they occur, rather than detecting and correcting them after the fact.
Solution Approach 2:
The patent implements feedback mechanisms through the coherency circuitry that continuously monitors the state of the write data cache and read data cache. This feedback information about buffer status, write dependencies, and cache coherence is used to dynamically control the reordering of access requests, ensuring that throughput optimization does not compromise data correctness.
3Adaptability or versatility
If memories are provided off-chip to support different memory types, then adaptability increases, but energy consumption and access latency increase
Solution Approach 1:
The patent segments the memory controller into separate write data cache and read data cache structures, each optimized for their specific access patterns. This segmentation allows the system to maintain frequently accessed data in on-chip cache memory, reducing the need for energy-consuming off-chip memory accesses while maintaining support for different memory types through the adaptable cache architecture.
Solution Approach 2:
The patent uses the coherency circuitry to perform preliminary assessment of memory access patterns and pre-fetch or cache data that is likely to be needed soon. This preliminary action reduces the frequency of off-chip memory accesses by keeping relevant data in the on-chip caches, thereby reducing energy consumption while maintaining adaptability to different memory types.
4Device complexity
If the interface between memory controller and memory is simplified, then device complexity decreases, but processing bottlenecks increase
Solution Approach 1:
The patent merges the write buffering and coherency management functions into an integrated write data cache structure with associated coherency circuitry. This merging consolidates multiple functions into unified structures, simplifying the overall controller interface while maintaining the capability to handle complex write operations, merge writes, and manage coherency without creating processing bottlenecks.
Data Source
AI summary
A memory controller includes a write data cache, a read data cache and coherency circuitry. The coherency circuitry manages coherency of data between the write data cache, the read data cache and data stored within a main memory when servicing read requests and write requests received by the memory controller. Write complete signals are issued back to a write requesting circuit as soon as a write request has had its write data stored within the write data cache.