Memory Controller Sequencer for NAND Flash Write Latency Reduction
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Solution Overview
Problem
Current memory systems face inefficiencies in writing operations, particularly in NAND flash memories, where data is written in multiple stages with long latency due to the need for repeated program and verify operations across multiple threshold levels, leading to prolonged busy states and increased latency.
Innovation Solution
The memory system employs a sequencer to manage write operations by executing program and verify loops based on threshold levels, allowing for divide writing strategies that terminate based on specific criteria such as threshold levels, program loop numbers, or processing time, enabling shorter busy states and reduced latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is written in multiple stages with repeated program and verify operations across multiple threshold levels, then data storage reliability is improved, but write operation time and latency are increased
Solution Approach 1:
The patent segments the write operation into multiple independent stages, each handling a specific threshold level. The sequencer divides the write command processing into discrete program loops that can be executed independently for different threshold levels (e.g., first threshold level, second threshold level). This segmentation allows the system to complete partial writes and return to idle state earlier, reducing overall latency while maintaining data integrity through staged verification.
2Measurement precision
If the sequencer executes complete program and verify loops for all threshold levels, then data accuracy is improved, but the busy state duration is increased
Solution Approach 1:
The patent implements partial action by allowing the sequencer to execute only a subset of the required program and verify loops before returning to idle state. Instead of completing all verification cycles for all threshold levels, the system performs partial writes at selected threshold levels and accepts that not all data pages will be fully verified in the first pass. This partial completion strategy significantly reduces busy state duration while still achieving acceptable data accuracy for critical operations.
3Reliability
If the memory system waits for all write operations to complete before accepting new commands, then data integrity is improved, but system responsiveness is worsened
Solution Approach 1:
The patent applies preliminary action by having the sequencer initiate and execute at least the first program loop for a write operation, then immediately return to idle state and accept subsequent write commands. The system performs preliminary verification at the first threshold level and prepares partial write results before the host system issues the next command. This allows overlapping of multiple write operations in the pipeline, improving system throughput and responsiveness while maintaining data integrity through staged completion and verification of each operation.
Data Source
AI summary
A memory system according to an embodiment includes a semiconductor memory and a memory controller. The semiconductor memory includes memory cells and a sequencer. Each of the memory cells stores first data when it has a first threshold voltage, and stores second data when it has a second threshold voltage. The sequencer performs a first write operation for write data. In the first write operation, the sequencer executes a program loop repeatedly and terminates the first write operation, when the verify operation for the first data has passed and the verify operation for the second data has not passed. The sequencer performs a second write operation for the write data based on a first command from the memory controller after the first write operation is terminated.