Memory Controller EDC Mode With Shared Parity Overhead Reduction
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Solution Overview
Problem
Existing memory systems face inefficiencies in error detection and correction due to high overhead in error-checking mechanisms, which occupy valuable bits and limit flexibility in data storage and encryption.
Innovation Solution
Implementing a low-overhead error detection and correction (EDC) mode that shares a single parity bit across multiple data words, freeing up bits for other uses and enabling error detection and correction for both data words and auxiliary bits, while also using auxiliary bits as a dynamic encryption seed for enhanced security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate parity bit is allocated for each data word, then error detection and correction capability is improved, but memory overhead increases and flexibility decreases
Solution Approach 1:
The patent merges the function of multiple separate parity bits into a single shared parity bit that serves all data words within a cache line. This consolidation reduces the total number of parity bits from N (one per word) to 1 (shared across all words), directly reducing memory overhead while maintaining error detection and correction capability through the extended syndrome generation mechanism.
Solution Approach 2:
The shared parity bit performs multiple functions: it enables error detection and correction for all data words in the cache line simultaneously, and the freed-up parity bit positions are repurposed to store auxiliary information such as encryption seeds. This multi-functionality resolves the contradiction by making the parity bit structure more versatile rather than dedicated to a single purpose.
2Reliability
If parity bits are used for error correction, then data integrity is improved, but availability for other uses such as encryption decreases
Solution Approach 1:
By merging multiple parity bits into a single shared parity bit, the patent frees up N-1 parity bit positions within each cache line. These freed positions are then combined with existing auxiliary bits to create a pool of available bits that can be used for encryption seeds, thereby increasing adaptability without sacrificing data integrity through the shared parity mechanism.
Solution Approach 2:
The patent creates a multi-functional bit structure where the shared parity bit handles error correction for all data words, while the previously dedicated parity bit positions are repurposed for dual use: maintaining error correction capability while simultaneously providing entropy for encryption seeds. This universality allows the same memory structure to serve both reliability and adaptability requirements.
3Measurement precision
If more bits are allocated for error checking, then error detection accuracy is improved, but storage efficiency decreases
Solution Approach 1:
The patent merges N separate error checking parity bits into 1 shared parity bit, reducing the total number of bits dedicated to error checking. This merging maintains error detection accuracy through extended syndrome generation that processes all data words against the shared parity bit, while simultaneously improving storage efficiency by freeing up N-1 bits for auxiliary data storage.
Solution Approach 2:
Instead of allocating full parity bits for every possible error scenario in each data word, the patent uses a single shared parity bit that provides sufficient error detection coverage for the entire cache line through extended syndrome analysis. This partial action approach achieves adequate error detection accuracy without the excessive bit allocation of traditional per-word parity schemes.
Data Source
AI summary
A memory controller is operable in an error detection/correction mode in which N syndrome values apply to N data words of a data volume, respectively, but a single parity bit is shared across all N data words of the data volume.