Memory Controller Shift Amount Table for Read Voltage Adaptation
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Solution Overview
Problem
Current memory systems face challenges in accurately determining data stored in memory cell transistors due to variations in threshold voltages, leading to errors in read operations, especially over time as data retention degrades.
Innovation Solution
A memory system with a memory controller that uses a shift amount table to adjust read voltages based on error correction analysis, estimating and updating shift amounts to optimize read operations and improve data reliability by correcting errors and adapting to changes in threshold voltage distributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed read voltages are used for memory operations, then the initial read accuracy is maintained, but read errors increase over time as threshold voltage distributions shift
Solution Approach 1:
The patent implements dynamic read voltage adjustment by storing multiple read voltages in a read voltage table and selecting appropriate voltages based on the program/erase cycle count of memory blocks. As threshold voltage distributions shift over time, the system adapts by choosing read voltages that account for these changes, thereby maintaining read accuracy throughout the memory device's operational life
Solution Approach 2:
The system changes the read voltage parameter based on the program/erase cycle count. By monitoring how many times memory blocks have been programmed and erased, the system adjusts the read voltage to compensate for threshold voltage shifts caused by wear, thus maintaining reliable data reading despite aging effects
2Measurement precision
If read voltage is adjusted frequently to maintain accuracy, then data reading precision improves, but operation complexity and time increase
Solution Approach 1:
The system performs preliminary actions by pre-calculating and storing appropriate read voltages in a read voltage table during manufacturing or initial operation. When reading data, the controller simply retrieves the pre-determined voltage from the table based on the program/erase cycle count, avoiding the need for time-consuming real-time voltage optimization calculations
Solution Approach 2:
The patent implements dynamic read voltage adjustment by storing multiple read voltages in a read voltage table and selecting appropriate voltages based on the program/erase cycle count of memory blocks. As threshold voltage distributions shift over time, the system adapts by choosing read voltages that account for these changes, thereby maintaining read accuracy throughout the memory device's operational life
3Reliability
If error correction is performed extensively, then data accuracy improves, but processing time and computational load increase
Solution Approach 1:
The system performs preliminary error correction by applying ECC to data immediately after reading from the memory device. By correcting errors in the first pass using pre-stored correction codes, the system retrieves most data without requiring repeated read operations or complex iterative correction algorithms, thus maintaining high processing speed
Solution Approach 2:
The system uses feedback from the error correction process to determine whether additional correction iterations are needed. If the first ECC pass successfully corrects errors, the system proceeds without further correction; if errors remain, the feedback triggers additional correction attempts, thus balancing accuracy with processing efficiency
Data Source
AI summary
According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.