Memory Controller Signal Period Adjustment for DDR Latching
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Solution Overview
Problem
As memory access speeds increase, signal quality deteriorates due to variations in printed circuit boards and pin specifications, making it challenging for memory controllers to adjust clock signals accurately within the small latching intervals of address and bank control signals, leading to errors and instability in DDR memory modules.
Innovation Solution
A memory controller and signal generating method that generates a first clock signal with a unit time period, a command signal with consecutive command groups, and an address signal with a period twice that of the unit time, allowing the clock signal edges to be set within the latching intervals of the command and address signals, effectively expanding the latching intervals and improving signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory access speed is increased to improve productivity, then signal quality deteriorates and latching intervals become smaller, making it difficult to adjust clock signals accurately
Solution Approach 1:
The patent applies dynamics by making the clock signal period adjustable rather than fixed. The memory controller dynamically adjusts the clock signal period to be twice the unit time period under certain conditions, allowing the system to adapt to different signal quality requirements while maintaining high memory access speed. This dynamic adjustment enables the clock signal edges to fall within the reduced latching intervals of control signals.
Solution Approach 2:
The patent changes the time period parameter of the clock signal from the unit time period to twice the unit time period. This parameter change effectively expands the latching intervals available for signal latching, allowing accurate signal capture even at high memory access speeds where latching intervals would otherwise be too small.
2Productivity
If memory access speed is increased, then the latching intervals of control signals become smaller, making it challenging to adjust clock signals accurately within those intervals
Solution Approach 1:
The system dynamically adjusts the clock signal period based on operational conditions. By switching to twice the unit time period when needed, the system creates larger time windows for clock signal edges to fall within the latching intervals, thereby improving adjustment precision without sacrificing overall memory access speed.
Solution Approach 2:
The patent utilizes periodic action by employing command groups with periodic patterns. The memory controller operates with periodic command sequences where every other command can utilize the expanded latching intervals provided by the doubled clock period, ensuring accurate signal latching while maintaining high throughput through the periodic structure.
3Reliability
If the clock signal period is doubled to expand latching intervals, then the signal period increases, but memory access speed may be affected
Solution Approach 1:
The patent resolves this contradiction by using periodic command groups where only every other command utilizes the doubled clock period. This periodic alternation allows the system to expand latching intervals when needed for reliable signal latching while maintaining faster access speeds for other operations, achieving both reliability and speed through time-multiplexed operation.
Solution Approach 2:
The system dynamically selects between unit time period and twice unit time period based on signal quality requirements and operational context. This dynamic period selection allows the memory controller to optimize between latching reliability and access speed on a per-command or per-condition basis, rather than being constrained to a single fixed period.
Data Source
AI summary
A memory controller and an associated signal generating method are provided. A generating sequence of commands is properly arranged to enlarge latching intervals of an address signal and a bank signal for stable access of a DDR memory module.