Memory Controller SLC Boost Block Address Mapping
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Solution Overview
Problem
Existing electronic systems face inefficiencies in read operations due to the need for hosts to search for physical addresses mapped to logical addresses, slowing down data retrieval processes.
Innovation Solution
Implementing a memory system with boost blocks configured for single-level cell programming and user blocks for multi-level cell programming, where the controller maps logical addresses to physical addresses and migrates data from boost blocks to user blocks during idle conditions, allowing for faster data retrieval by omitting the search for physical addresses during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the host searches for physical addresses mapped to logical addresses during read operations, then the read operation can be performed, but the read speed is reduced due to the address search process
Solution Approach 1:
The patent applies preliminary action by having the host store the physical address in a buffer memory during the program operation, before the read operation is needed. This pre-stored physical address is then directly used during the read operation, eliminating the need for address search and thereby improving read speed while reducing the time loss associated with address lookup.
2Productivity
If data is stored in boost blocks using SLC method, then programming speed is improved, but storage capacity is reduced compared to MLC/TLC/QLC methods
Solution Approach 1:
The patent applies segmentation by dividing the storage system into two distinct types of memory blocks: boost blocks using SLC method for fast programming operations, and user blocks using MLC/TLC/QLC methods for high-capacity storage. This segmentation allows the system to leverage the speed advantage of SLC when needed while maintaining the high storage capacity of multi-level cell methods, thus resolving the contradiction between programming speed and storage capacity.
Solution Approach 2:
The patent applies local quality by assigning different storage characteristics to different physical locations within the memory system. Boost blocks are optimized for speed with SLC characteristics, while user blocks are optimized for capacity with MLC/TLC/QLC characteristics. This local differentiation allows each region to serve its specific purpose, enabling the system to achieve both fast programming and high storage capacity simultaneously.
3Quantity of substance
If data is migrated from boost blocks to user blocks, then storage capacity utilization is improved, but additional operations are required
Solution Approach 1:
The patent applies self-service by implementing an automatic data migration mechanism where the controller autonomously transfers data from boost blocks to user blocks based on predefined conditions, such as when boost blocks are full or when user blocks become available. This automated process eliminates the need for manual intervention or complex external control, thereby improving storage capacity utilization while managing the complexity of data migration operations internally within the memory system.
Data Source
AI summary
The present technology includes a host configured to output a program request, a logical address, and data during a program operation, and a memory system configured to map a first physical address to the logical address, program the data to first memory blocks corresponding to the first physical address in a single level cell (SLC) method, program the data stored in the first memory blocks to a second memory block in a higher level cell method including a multi-level cell (MLC) method, a triple level cell (TLC) method, or a quadruple level cell (QLC) method after changing the first physical address to a second physical address, and transmit the second physical address to the host. The host outputs a read request and the second physical address to the memory system during a read operation of the data corresponding to the logical address.