Memory Controller SLC Erase for Mixed Mode Blocks

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Solution Overview

Problem

Existing memory management techniques face challenges in achieving high endurance and performance, particularly in multi-cursor dynamic SLC cache architectures, where previous approaches often rely on single SLC write trims and fail to balance endurance and wear ratio effectively, leading to inefficiencies and instability.

Innovation Solution

The implementation of a memory management system that includes a controller configured to identify mixed mode blocks and perform erase operations in SLC mode, reducing endurance requirements and erase latencies, and allocating memory blocks into different groups for optimal performance and endurance, with a single SLC trim set used to manage both SLC and XLC modes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If single SLC write trims are used in multi-cursor dynamic SLC cache architectures, then device complexity is reduced, but endurance and wear ratio balance deteriorates

Engineering Contradiction:

Improvememory management complexityVSAvoidendurance and wear ratio balance

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent segments the SLC cache management into multiple independent trim sets (first SLC trim set and second SLC trim set) that can be selectively applied to different memory blocks based on their intended usage mode. This segmentation allows the system to maintain simple management protocols while achieving differentiated optimization for SLC and XLC modes, thereby resolving the contradiction between device complexity and reliability.

Inventive Principle:

Principle #1Segmentation

2Ease of operation

If mixed mode blocks are not differentiated by erase mode, then ease of operation is improved, but performance and endurance are compromised

Engineering Contradiction:

Improvememory block managementVSAvoidwrite performance and endurance

Core Design Contradiction:

Ease of operationVSProductivity

Solution Approach 1:

The patent implements dynamic trim set selection where the controller automatically determines whether to apply the first or second SLC trim set based on the intended usage mode (SLC or XLC) of each memory block. This dynamic adaptation allows the system to maintain ease of operation with automatic mode detection while achieving optimized performance and endurance through mode-specific trim parameters.

Inventive Principle:

Principle #15Dynamics

3Use of energy by moving object

If erase operations are not performed in SLC mode for mixed mode blocks, then use of energy is reduced, but endurance requirements and erase latencies increase

Engineering Contradiction:

Improveerase operation energyVSAvoiderase latency

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The patent changes the erase operation parameters by introducing two distinct SLC trim sets with different characteristics. The first SLC trim set is specifically optimized for mixed mode blocks that will be used in SLC mode, enabling faster and more energy-efficient erase operations. This parameter change allows the system to reduce erase latency and improve energy efficiency for SLC-mode blocks without compromising XLC mode functionality.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11586357B2Memory management

Publication Date: 2023.02.21 MICRON TECHNOLOGY INC

AI summary

The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.