Memory Controller Alternating SLC and MLC Operations
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Solution Overview
Problem
Conventional memory devices using multi-level cells face disturbance errors due to heat transfer during repeated state changes, which affects data storage reliability and efficiency.
Innovation Solution
A memory controller is configured to alternate between single-level and multi-level cell operations based on intermediate state conditions, using different mapping schemes to mitigate heat transfer by separating data across word lines, thereby expanding the resistance margin and reducing disturbance errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell operations are used to increase storage capacity, then data storage capacity is improved, but disturbance errors increase due to heat transfer during repeated state changes
Solution Approach 1:
The patent segments the memory system into two distinct operational modes: single-level cell operations and multi-level cell operations. This segmentation allows the system to use SLC operations for frequently accessed or critical data that requires high reliability, while using MLC operations for less critical data where storage capacity is prioritized. The memory controller dynamically assigns different data blocks to different operational modes based on their reliability requirements.
Solution Approach 2:
The patent changes the operational parameters of the memory cells by alternating between two distinct operation modes. Single-level cell operations use one set of programming parameters with larger resistance margins and lower heat generation, while multi-level cell operations use different parameters that achieve higher density but with smaller resistance margins and higher heat generation. This parameter switching resolves the contradiction by allowing the system to optimize for either capacity or reliability depending on the specific data requirements.
2Adaptability or versatility
If repeated state changes are performed in multi-level cells, then data storage flexibility is improved, but heat transfer increases causing disturbance errors
Solution Approach 1:
The patent extracts the harmful heat generation effect from the overall memory operation by identifying it as a characteristic specific to multi-level cell operations. By separating MLC operations from SLC operations, the system can take out the heat transfer problem and apply appropriate mitigation strategies only where needed, such as using enhanced error correction for MLC data or reducing the frequency of state changes in MLC cells.
Solution Approach 2:
The patent implements dynamic operation mode selection where the memory controller can switch between single-level and multi-level cell operations based on real-time conditions. This dynamic approach allows the system to adapt to varying workloads and thermal conditions, selecting SLC mode when heat management is critical and MLC mode when storage capacity and flexibility are prioritized, thereby resolving the contradiction between adaptability and heat-induced disturbances.
3Reliability
If single-level cell operations are used, then resistance margin is improved, but data storage capacity is reduced
Solution Approach 1:
The patent merges two previously separate memory systems into a unified hybrid architecture. Both single-level cell and multi-level cell operations share the same physical memory array and controller resources, but operate in different modes. This merging allows the system to achieve the benefits of both SLC (high resistance margin) and MLC (high storage capacity) operations within a single system, allocating data to appropriate operational modes based on their specific requirements rather than forcing a choice between the two approaches.
Data Source
AI summary
Multi-level cell memory management techniques are described. In one example, the memory controller is configured to control whether a single-level cell operation or a multi-level cell operation to be used using different mapping schemes. The single-level cell operation, for instance, is usable to store a data word using two states whereas the multi-level cell operation is usable to store the data word by also using an intermediate state. In order to store the data word using two states, the memory controller is configurable to separate the data word across two word lines in the physical memory. In an implementation, use of the different operations and corresponding mapping schemes by the memory controller alternates between adjacent word lines in physical memory.