Non-volatile Memory Controller Sleep State Data Retention
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Solution Overview
Problem
Conventional flash memory devices face challenges in efficiently managing power states to reduce power consumption and maintain data integrity during transitions between active and sleep states without the need for a power switch, leading to increased processing time and communication delays.
Innovation Solution
A non-volatile semiconductor memory device with a controller that includes a reset terminal, interface circuit, and data storing circuit, capable of receiving reset and sleep commands, allowing for selective power interruption and resumption while storing necessary data, enabling seamless transitions between power states without erasing critical communication settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power supply is turned off to reduce power consumption, then power consumption is reduced, but processing time increases during state transitions
Solution Approach 1:
The patent applies preliminary action by storing communication settings and data in a data storing circuit before power interruption occurs. When the controller receives a sleep command, it proactively saves necessary communication parameters (such as UFS host settings) to the data storing circuit before cutting power to the interface circuit. This pre-storation eliminates the need to re-establish communication settings after power restoration, thereby reducing processing time during state transitions while maintaining low power consumption during sleep mode.
2Ease of operation
If power switch is added to control power supply selectively, then power control precision is improved, but device complexity increases
Solution Approach 1:
The patent applies self-service by implementing power state management through software control rather than additional hardware switches. The controller autonomously manages power states by receiving sleep commands, storing necessary data in the data storing circuit, and controlling power interruption to the interface circuit through internal power control logic. This approach achieves precise power control without adding external power switches, thereby maintaining ease of operation while avoiding increased device complexity.
3Use of energy by moving object
If power is interrupted to interface circuit to save power, then power consumption is reduced, but communication recovery time increases
Solution Approach 1:
The patent applies preliminary action by pre-storing communication settings and data in the data storing circuit before power interruption. When the interface circuit is powered down to save energy, the controller has already saved critical communication parameters (such as UFS host communication settings) to the data storing circuit. Upon power restoration, the controller can immediately retrieve these pre-stored settings rather than re-establishing communication from scratch, thereby significantly reducing communication recovery time while maintaining low power consumption during sleep mode.
Data Source
AI summary
The non-volatile semiconductor memory device comprises a non-volatile semiconductor memory, a controller for controlling the non-volatile semiconductor memory, the controller includes a reset terminal capable of receiving a reset signal from a host, an interface circuit capable of receiving a sleep command, and a data storing circuit, when the reset signal is received in a state which the interface circuit is being supplied with power, the data storing circuit is reset, when a sleep command is received in a state which the interface circuit is being supplied with power, the data necessary for communication with the host or the non-volatile semiconductor memory device is stored into the data storing circuit and power to the interface circuit is interrupted and when the reset signal is received in a state which power to the interface circuit is interrupted, the data is read from the data storing circuit.