Memory Controller Sleep Mode Power Stop Detection

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Solution Overview

Problem

Existing memory systems lack an efficient method to determine if power has been stopped while in sleep mode, leading to potential data loss and unnecessary resets.

Innovation Solution

A memory system with a controller that operates using a second voltage, allowing it to check operation information stored in a non-volatile first storage region and selectively reset the memory device based on whether the first voltage was stopped, ensuring accurate wake-up and operation state management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the memory device enters sleep mode to reduce power consumption, then power consumption is reduced, but the system cannot reliably determine whether power was stopped during sleep mode

Engineering Contradiction:
Improvepower consumptionVSAvoidpower stop detection accuracy
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The system performs preliminary actions by storing operation information in the memory device before entering sleep mode, and prepares a detection mechanism that will check whether power was stopped during sleep mode upon wake-up. This allows the system to proactively manage power state detection rather than reactively handling power loss scenarios.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The controller acts as an intermediary between the host and memory device, checking operation information to determine whether power was stopped during sleep mode. The controller mediates the power management process by interpreting the state of operation information and deciding whether a reset is necessary, thereby resolving the contradiction between power savings and reliable detection.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the memory device performs a reset upon wake-up to ensure data integrity, then data integrity is improved, but unnecessary resets occur when power was not actually stopped

Engineering Contradiction:
Improvedata integrityVSAvoidoperation efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system implements feedback by checking the state of operation information stored in the memory device after wake-up. Based on this feedback, the controller determines whether a reset is actually necessary. This feedback mechanism prevents unnecessary resets while ensuring data integrity when power was genuinely stopped, thereby resolving the contradiction between reliability and productivity.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The memory device serves itself by maintaining operation information internally in its own storage regions during sleep mode. The controller then uses this self-maintained information to make autonomous decisions about whether resetting is needed, eliminating the need for external intervention or conservative reset policies that would reduce productivity.

Inventive Principle:
Principle #25Self-service

3Measurement precision

If the controller checks operation information to determine power stop status, then power stop detection accuracy is improved, but system complexity increases

Engineering Contradiction:
Improvepower stop detection accuracyVSAvoidsystem complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The controller performs multiple functions: it manages normal memory operations, handles sleep mode transitions, checks operation information for power stop detection, and decides on reset necessity. By making the controller universal and multi-functional, the patent avoids adding separate dedicated detection hardware, thereby improving measurement precision while minimizing the increase in system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system uses copies of operation information stored in different storage regions of the memory device to detect power stop status. Rather than adding complex detection circuitry, the system leverages existing memory structures and their state (reset vs. non-reset values) to infer power conditions, achieving accurate detection with minimal added complexity.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS9804860B2Memory system having sleep mode and wake up mode and operation method thereof
Publication Date: 2017.10.31 SK HYNIX INC
  • US9804860B2 patent drawing
  • US9804860B2 patent drawing
  • US9804860B2 patent drawing

AI summary

A memory system may include: a memory device that operates using a first voltage received from a host and suitable for storing a value of operation information, and waking up from a sleep state in response to a request of the host; and a controller that operates using a second voltage received from the host, and suitable for selectively resetting the memory device according to a result obtained by checking a value of operation information of the memory device, when waking up the memory device in a sleep state according to a request of the host.