Memory Controller Data Stream Dispatch for Smart Card Integration

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Solution Overview

Problem

Existing methods fail to accurately identify and transmit data streams between a host system and a smart card chip in memory storage apparatuses with non-volatile memory, leading to inefficiencies in data management and storage.

Innovation Solution

A method involving configuring logical block addresses for non-volatile memory, receiving and storing response data units in a buffer memory, and determining whether these units belong to specific logical block addresses to ensure correct transmission to the host system, utilizing a memory controller with a memory interface, host interface, and buffer memory to manage data streams.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a memory storage apparatus combines non-volatile memory and smart card chip to expand storage capacity and functionality, then the storage capacity and security functions are improved, but the complexity of identifying and transmitting data streams between the host system and smart card chip increases

Engineering Contradiction:
Improvestorage capacity and security functionsVSAvoiddata stream identification and transmission complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments data streams into distinct types (command data units and response data units) and assigns them to different logical block addresses. This segmentation allows the memory controller to identify and route different data types through separate pathways, reducing the complexity of managing mixed data streams while maintaining the enhanced functionality of the combined memory and smart card system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a memory controller as an intermediary component that mediates between the host system and the smart card chip. This intermediary manages the data stream transmission by determining whether received data belongs to command or response types based on logical block addresses, thereby simplifying the interaction complexity between the host and smart card components.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the memory controller receives and processes all data streams from the host system and smart card chip, then data management capability is improved, but the processing time and response speed decrease

Engineering Contradiction:
Improvedata management capabilityVSAvoiddata processing time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements preliminary action by pre-configuring specific logical block addresses for command data units and response data units. This pre-arrangement allows the memory controller to quickly determine the type of incoming data through simple address comparison rather than complex analysis, thereby improving data management capability while reducing processing time.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses parameter changes by varying the logical block address values to encode different data types. By changing the address parameter based on data type (specific addresses for commands vs. specific addresses for responses), the system achieves efficient data management with minimal processing overhead, as the memory controller only needs to compare address parameters rather than analyze data content.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8812756B2Method of dispatching and transmitting data streams, memory controller and storage apparatus
Publication Date: 2014.08.19 PHISON ELECTRONICS
  • US8812756B2 patent drawing
  • US8812756B2 patent drawing
  • US8812756B2 patent drawing

AI summary

A method of dispatching and transmitting data stream, which is used for a memory storage apparatus having a non-volatile memory module and a smart card chip, is provided. The method includes configuring a plurality of logical block addresses, and a plurality of specific logical block addresses are used for storing a specific file. The method also includes receiving a response data unit from the smart card chip and storing the response data unit in a buffer memory. The method also includes, when a logical block address corresponding to a read command from a host system belongs to one of the specific logical block addresses and the buffer memory stores a response data unit, transmitting the response data unit stored in the buffer memory to the host system. Accordingly, the method can make the host system to correctly receive the response data unit from the smart card chip.