Memory Controller Soft Decision Read Data Generation
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Solution Overview
Problem
Multilevel cell (MLC) non-volatile memory devices face challenges in precise data reading due to overlapping threshold voltage distributions, leading to increased read failure rates and errors as the number of bits programmed in each memory cell increases, caused by charge loss and program disturbance.
Innovation Solution
A controller and semiconductor memory system that employs soft decision read data generation and ECC decoding using LDPC decoding, de-scrambling, and ECC encoding to improve data reading accuracy by utilizing soft decision read voltages and log likelihood ratios (LLR) for error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits programmed in each memory cell increases to achieve high integration, then storage capacity is improved, but reliability decreases and read failure rate increases due to overlapping threshold voltage distributions
Solution Approach 1:
The patent applies parameter changes by transitioning from hard decision read (binary 0/1) to soft decision read (multi-level confidence values). This changes the reading parameter from simple threshold comparison to probabilistic confidence assessment, enabling the system to handle overlapping threshold voltage distributions in MLC memory by providing graded confidence levels rather than binary decisions.
Solution Approach 2:
The patent introduces Log Likelihood Ratio (LLR) values as an intermediary between the physical threshold voltage and the logical data bit. The LLR provides a probabilistic bridge that translates analog threshold voltage measurements into reliable digital decisions, even when threshold distributions overlap, thereby maintaining high reliability in high-capacity MLC memory.
2Reliability
If soft decision read data generation and ECC decoding are employed to improve data reading accuracy, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the error correction process into distinct functional modules: soft decision read data generation unit, de-scrambling unit, and ECC decoding unit. This segmentation allows each component to be optimized independently and facilitates parallel processing, reducing the practical complexity impact despite the advanced functionality implemented.
Solution Approach 2:
The patent performs de-scrambling operation before ECC decoding as a preliminary action. This preprocessing step prepares the soft decision data in an optimal format for subsequent error correction, allowing the ECC decoder to operate more efficiently and reducing the overall computational complexity of the system.
Data Source
AI summary
An operating method of a memory controller includes: generating a soft decision read data for stored data read from a semiconductor memory device according to a soft decision read voltage, wherein the stored data is stored in the semiconductor memory device through sequential operations of ECC encoding and scrambling; and generating a first de-scrambled data by performing de-scrambling operation to a sign bit of the soft decision read data.