Memory Controller Soft Read Voltage Tuning for MLC ECC Recovery
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Solution Overview
Problem
In semiconductor memory devices, especially multi-level cell (MLC) flash memory, the overlap of threshold voltage distributions due to charge loss and characteristic deterioration leads to increased read errors as the number of bits programmed in each memory cell increases, making precise determination of optimal read voltages challenging.
Innovation Solution
A controller and method that generate optimization information including deterioration information, ECC decoder parameters, and constituent code parameters to determine quantization intervals, allowing for a second ECC decoding operation using soft read voltages, which improves the reliability of error correction and reduces read errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit data is programmed in each memory cell to increase storage capacity, then integration density is improved, but threshold voltage distributions overlap and read error rates increase
Solution Approach 1:
The patent changes the parameter of read voltage from a single fixed value to multiple quantized voltage levels. By applying different read voltages (Vread1, Vread2, Vread3) corresponding to different quantization intervals, the system can distinguish between overlapping threshold voltage distributions of multi-bit memory cells, thereby reducing read errors while maintaining high storage capacity
Solution Approach 2:
The patent segments the continuous threshold voltage distribution into discrete quantization intervals. By dividing the voltage range into multiple intervals and assigning each interval to a specific data state, the system can accurately determine the stored data even when threshold voltage distributions overlap, thus resolving the contradiction between high-density storage and read reliability
2Productivity
If the number of program and erase operations increases to utilize more memory blocks, then storage utilization is improved, but charge loss accelerates and threshold voltage distributions shift
Solution Approach 1:
The patent performs preliminary determination of quantization intervals based on deterioration information before actual read operations. By pre-calculating the appropriate read voltages and quantization intervals according to the memory block's wear state, the system proactively compensates for threshold voltage shifts caused by charge loss, ensuring accurate reads even after numerous program-erase cycles
Solution Approach 2:
The patent implements a feedback mechanism where deterioration information (such as program-erase cycle count) is continuously monitored and used to adjust the quantization intervals and read voltages. This feedback loop allows the system to adapt to changing threshold voltage distributions over time, maintaining read reliability as storage utilization increases
3Speed
If hard decision ECC decoding is used for fast error correction, then decoding speed is improved, but correction capability is insufficient when threshold voltage distributions overlap
Solution Approach 1:
The patent introduces a dynamic decoding approach that adapts the decoding method based on the determined data state. After determining the quantization interval and corresponding read voltage, the system dynamically selects appropriate ECC decoding parameters and methods, transitioning from static hard decision decoding to more sophisticated soft decision decoding when needed, thereby achieving both speed and reliability
Data Source
AI summary
An operating method of a controller, comprising:generating, when a first ECC decoding operation to codeword read from a semiconductor memory device according to a hard read voltage fails, an optimization information corresponding the result of the first ECC decoding operation; generating one or more quantization intervals determined by the optimization information; and performing a second ECC decoding operation to codeword read from the semiconductor memory device according to soft read voltages determined by the quantization intervals and the hard read voltage, wherein the optimization information includes: deterioration information of a memory block; ECC decoder parameter information; and constituent code parameter information.