Memory Controller Vector Scheduling for Sparse Matrix Multiplication
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Solution Overview
Problem
Existing memory controllers face inefficiencies in performing calculations due to long operation times and high power consumption when handling high-capacity data, particularly in matrix multiplications involving sparse matrices.
Innovation Solution
A memory controller with multiple computing units and a controller that identifies vectors required for matrix multiplication operations, allowing sequential input of vectors into these units based on specific information, thereby optimizing calculations and reducing the number of memory accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory controller performs calculations using data stored in memory, then calculation performance can be improved, but the operation time becomes long
Solution Approach 1:
The patent divides the calculation process into multiple stages: identifying non-zero element positions in the sparse matrix, retrieving corresponding vectors from memory, and performing calculations. This segmentation allows optimization of each stage independently, particularly by reducing memory access frequency through efficient data organization and processing strategies.
Solution Approach 2:
The patent performs preliminary identification of non-zero element positions and their corresponding vector indices before actual calculation. This preliminary action prepares the data structure in advance, allowing the calculation unit to process data more efficiently without repeated memory accesses during the calculation phase.
2Measurement precision
If the memory controller reads data from memory for calculations, then calculation accuracy is maintained, but power consumption increases
Solution Approach 1:
The patent extracts only the necessary vectors corresponding to non-zero elements from the sparse matrix for calculation, rather than processing the entire matrix. This extraction approach maintains calculation accuracy by focusing on relevant data while significantly reducing the amount of data transferred and processed, thereby lowering power consumption.
Solution Approach 2:
The patent changes the representation parameters of the sparse matrix by organizing data according to non-zero element positions and their corresponding vector indices. This parameter transformation enables more efficient memory access patterns and reduces the volume of data that needs to be read and processed, achieving both accuracy and energy efficiency.
3Productivity
If the memory controller processes high-capacity data, then calculation capability is enhanced, but the number of operations increases
Solution Approach 1:
Instead of processing the sparse matrix in its traditional format, the patent inverts the approach by organizing processing around non-zero elements and their corresponding vectors. This inversion reduces the number of operations by eliminating processing of zero elements and optimizing the calculation flow to match the sparse data structure's inherent properties.
Data Source
AI summary
A memory controller includes a plurality of computing units and a controller. The plurality of computing units perform calculations related to a matrix multiplication. The controller identify first information indicating a plurality of vectors required for the calculations with respect to a plurality of rows of a matrix, identify second information indicating at least one row to which each of the plurality of vectors corresponds among the plurality of rows, and control the plurality of computing units to perform the calculations with respect to the plurality of rows by sequentially inputting the plurality of vectors into the plurality of computing units based on the first information and the second information.