Memory Controller Spatial Redundancy for 3D Stacked DRAM Failures
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Solution Overview
Problem
Current 3D stacked DRAM designs face challenges with new error models, such as through silicon via failures and chip failures, which lead to significant capacity and bandwidth losses due to weak fault tolerance, especially in high granularity failures, making it difficult to recover data when failures occur in stacks connected to a single compute unit.
Innovation Solution
A memory system with a memory controller that divides data into sub-blocks and creates a reliability sub-block, writing these sub-blocks across multiple memory stacks, allowing for error detection and recovery by using data-co-located ECC and spatial redundancy, ensuring that correct data can be recovered even if one stack fails.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If data is stored in 3D stacked DRAM with traditional ECC, then energy efficiency is improved, but fault tolerance deteriorates
Solution Approach 1:
The memory system is segmented into multiple independent stacks, each capable of storing portions of data. This segmentation allows the system to isolate failures to individual stacks while maintaining access to data in other stacks, thereby improving fault tolerance without requiring complex global error correction mechanisms that would increase energy consumption.
Solution Approach 2:
A memory controller acts as an intermediary between the compute unit and multiple memory stacks. It manages data distribution across stacks, handles error detection and recovery, and coordinates read/write operations. This intermediary layer enables sophisticated fault tolerance management while keeping individual stack designs simple and energy-efficient.
2Productivity
If multiple memory stacks are connected to a single compute unit, then memory bandwidth is improved, but reliability deteriorates
Solution Approach 1:
Data is segmented and distributed across multiple memory stacks connected to a single compute unit. Each stack operates independently, so if one stack fails, the compute unit can continue accessing data from remaining stacks through the memory controller, maintaining system reliability while preserving high bandwidth capabilities.
Solution Approach 2:
The system dynamically changes operational parameters such as data distribution patterns and access routing based on stack health status. When a stack failure is detected, the memory controller adjusts data routing parameters to bypass failed stacks, maintaining reliable operation while preserving bandwidth through optimized data paths.
3Reliability
If data is distributed across multiple memory stacks, then fault tolerance is improved, but bandwidth overhead increases
Solution Approach 1:
The system implements partial redundancy by storing data across multiple stacks without requiring complete duplication. The memory controller intelligently determines the minimum necessary data distribution to achieve acceptable fault tolerance levels, avoiding excessive bandwidth consumption while maintaining adequate reliability through selective data placement and intelligent read routing.
Data Source
AI summary
Memory management circuitry and processes operate to improve reliability of a group of memory stacks, providing that if a memory stack or a portion thereof fails during the product's lifetime, the system may still recover with no errors or data loss. A front-end controller receives a block of data requested to be written to memory, divides the block into sub-blocks, and creates a new redundant reliability sub-block. The sub-blocks are then written to different memory stacks. When reading data from the memory stacks, the front-end controller detects errors indicating a failure within one of the memory stacks, and recovers corrected data using the reliability sub-block. The front-end controller may monitor errors for signs of a stack failure and disable the failed stack.