Memory Controller SPO Command Prioritization

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Solution Overview

Problem

Current memory systems face challenges in minimizing the time required to dump data and recover from sudden power off (SPO) events, as they often involve aborting operations and prioritizing data recovery, which can prolong the process.

Innovation Solution

Implementing a memory controller that identifies and enqueues a target command for writing meta-data into a top priority command queue before SPO, allowing it to be processed before entering a power-off state, and reordering command execution to ensure critical operations are completed efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If the memory system permits continued execution of operations during SPO to minimize dump time, then data dump speed is improved, but system complexity increases due to operation management and abort mechanisms

Engineering Contradiction:
Improvedata dump timeVSAvoidoperation management complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-identifying and prioritizing critical operations before SPO occurs. The memory controller classifies operations as critical or non-critical and pre-configures priority command queues, so that during SPO, the system can immediately execute critical operations without complex real-time decision-making, thus reducing dump time while managing complexity through advance planning

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments operations into critical and non-critical categories, and divides command queues into regular queues and priority queues. This segmentation allows the system to handle only essential operations during SPO in the priority queue, minimizing dump time while simplifying management by clearly separating what must be executed from what can be aborted

Inventive Principle:
Principle #1Segmentation

2Productivity

If the memory system aborts non-critical operations during SPO to speed up data dump, then productivity is improved, but reliability may worsen due to potential data loss

Engineering Contradiction:
Improvedata dump speedVSAvoiddata integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system performs preliminary classification of operations into critical and non-critical types before SPO occurs. Critical operations that must be completed for data integrity are identified in advance and placed in priority command queues, ensuring they are executed during SPO even as non-critical operations are aborted, thus maintaining reliability while improving dump speed

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces priority command queues as an intermediary mechanism between regular operation queues and the execution engine. This intermediary structure filters and prioritizes critical operations, allowing the system to abort non-critical operations for faster dumping while ensuring critical operations are preserved and executed, thereby maintaining data integrity

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of operation

If the memory controller uses multiple priority command queues to manage operations, then ease of operation is improved, but device complexity increases

Engineering Contradiction:
Improvecommand prioritization easeVSAvoidqueue management complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent applies local quality by creating different types of command queues with different priorities (regular queues and priority queues). Each queue type has specific characteristics optimized for its purpose: regular queues for normal operations and priority queues for critical SPO operations. This localized differentiation simplifies operation management within each queue type while the overall system handles complexity through clear hierarchical structure

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11409470B2Memory system, memory controller, and method of operating memory system
Publication Date: 2022.08.09 SK HYNIX INC
  • US11409470B2 patent drawing
  • US11409470B2 patent drawing
  • US11409470B2 patent drawing

AI summary

Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the memory system. According to the embodiments of the present disclosure, the memory system may search for a target command, to be processed before entering a power-off state, in a plurality of command queues that queue commands to be inputted to the memory device when a sudden power off (SPO) signal is transmitted from a power management core to a flash interface layer core, may enqueue the target command into a top priority command queue having the highest priority among the plurality of command queues, and may input the target command enqueued into the top priority command queue to the memory device before entering the power-off state.