Memory Controller Spread Spectrum Clocking for EMI Reduction
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Solution Overview
Problem
High-frequency clock signals in electronic devices generate significant electromagnetic interference, affecting the operation of adjacent circuits due to the high peak levels of electromagnetic interference caused by control and address signals transmitted to synchronous memory.
Innovation Solution
A memory controller with a reference clock generator and a memory control portion that outputs control commands and address signals during extended periods synchronized with modulated clocks, reducing the frequency and duration of high-interference signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-frequency clock signals are used to increase processing speed, then the processing speed is improved, but electromagnetic interference increases
Solution Approach 1:
The patent applies spread spectrum clock technology that periodically modulates the clock frequency by a few percent, transforming the continuous high-frequency signal into a periodically varying signal. This periodic modulation spreads the electromagnetic energy across a frequency range, reducing peak interference levels while maintaining the average processing speed.
Solution Approach 2:
The patent changes the frequency parameter of the clock signal by modulating it according to spread spectrum technology. The clock frequency is dynamically adjusted within a narrow band, transforming the signal characteristics to reduce electromagnetic interference while preserving the essential timing function for high-speed processing.
2Speed
If control signals and address signals are transmitted during one clock cycle, then the memory operation speed is improved, but the peak level of electromagnetic interference becomes too high
Solution Approach 1:
The patent extends the transmission period of control signals and address signals beyond one clock cycle, using periodic modulation to spread the signal energy. This approach reduces the instantaneous peak power while maintaining the overall data transmission rate through optimized timing sequences.
Solution Approach 2:
The patent dynamically adjusts the timing and duration of signal transmission, extending it over multiple clock cycles when necessary. This dynamic timing adjustment allows the system to maintain high operational speed while controlling peak interference levels by distributing the signal energy over time.
3Productivity
If clock frequency is increased to 100 MHz or higher, then the system performance is improved, but electromagnetic interference from address bus becomes significant
Solution Approach 1:
The patent changes the frequency characteristics of the address bus signals by applying spread spectrum modulation. This transforms the sharp high-frequency components into a broader, lower-peaked frequency spectrum, allowing 100 MHz or higher clock frequencies to operate with reduced electromagnetic interference on the address bus.
Solution Approach 2:
The patent uses periodic frequency modulation of the clock signal to spread the electromagnetic energy from the address bus over a wider frequency range. This periodic action reduces the concentration of energy at any single frequency, thereby reducing overall electromagnetic interference while maintaining high system performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces electromagnetic interference by lowering the peak levels of control and address signals, thereby minimizing adverse effects on adjacent circuits and improving the operational reliability of electronic devices.
Implementation Method 1
a reference clock generator for generating reference clocks having a predetermined frequency
Implementation Method 2
The memory control portion reads data from a synchronous memory in synchronization with the reference clocks
Implementation Method 3
a control command generator for outputting a control command to the synchronous memory during an output period of time
Implementation Method 4
an address signal generator for outputting an address signal to the synchronous memory during a first period of time, the first period of time including the output period of time and being longer than the output period of time
Implementation Method 5
outputs control commands and address signals during extended periods synchronized with modulated clocks, reducing the frequency and duration of high-interference signals
Implementation Method 6
This solution effectively reduces electromagnetic interference by lowering the peak levels of control and address signals
Data Source
AI summary
In order to output an active command to an SDRAM, at time t0, output of a valid row address starts and a control signal ras# enters the active state. Thereafter, a control signal cs# enters the active state at time t1. At time t3, the signal cs# returns to the negative state. At time t4 when some period of time has passed after time t3, output of the valid row address stops and the signal ras# enters the negative state. Outputs of the address signal adr and the control signals ras#, cas# and we# are controlled in synchronization with a modulated clock S-clk, which is generated at the spread spectrum generator. This reduces the electromagnetic interference that is caused by the address signal adr and the control signals ras#, cas# and we#.