High Reliability Memory Controller for Stacked Die Packages
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Solution Overview
Problem
Integrated circuits with stacked memory chips face reliability issues due to faults such as bit corruption from background radiation and electromigration, leading to costly replacements of entire packages when a single memory chip fails.
Innovation Solution
A high reliability memory controller that stores both data and reliability information in standard memory chips, using error correction codes to detect and correct errors, allowing for selective correction and recreation of data elements across multiple memory banks, thereby enhancing system reliability and serviceability without adding memory chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standard memory chips are used in stacked die configurations, then integration density and performance are improved, but reliability deteriorates due to susceptibility to faults from background radiation and electromigration
Solution Approach 1:
The patent applies preliminary action by proactively storing reliability information (ECC codes) alongside data elements before faults occur. The memory controller continuously maintains redundancy information that can be immediately used for error correction when radiation-induced bit flips or electromigration faults happen, preventing data loss without requiring preventive replacement of memory chips.
Solution Approach 2:
The patent implements beforehand cushioning by creating a protective layer of redundancy through error correction codes. This cushioning mechanism absorbs the impact of faults from background radiation and electromigration, allowing the system to tolerate these harmful effects without catastrophic failure. The ECC information acts as a buffer that compensates for the inherent unreliability of stacked memory chips.
2Reliability
If a memory chip in a stacked die package fails, then system reliability is maintained through redundancy, but ease of repair deteriorates because the entire package must be replaced
Solution Approach 1:
The patent applies segmentation by logically separating the functionality of individual memory chips within the stacked package. Each memory chip is treated as an independent replaceable unit with its own associated reliability information. When a fault occurs in one chip, the system can identify and replace only that specific chip rather than the entire package, because the control logic and ECC mechanisms are organized at the chip level.
Solution Approach 2:
The memory controller serves as an intermediary that manages the relationship between multiple memory chips and the processor. It monitors reliability information from each chip, identifies faulty chips, and coordinates replacement operations. This intermediary layer enables selective replacement of individual failed chips while maintaining system reliability, bridging the gap between physical chip failures and system-level fault tolerance.
3Reliability
If error correction codes are stored in separate memory locations, then reliability is improved through detection and correction capability, but device complexity increases due to additional memory requirements
Solution Approach 1:
The patent applies merging by combining data elements and their associated reliability information (ECC codes) into unified memory structures. Instead of maintaining completely separate storage for data and error correction information, the system integrates them in a coordinated manner within the same memory banks, reducing the overhead of duplicate memory structures while maintaining full error correction capability.
Solution Approach 2:
The memory controller implements multi-functionality by using the same memory infrastructure for both data storage and reliability information storage. The memory banks serve dual purposes: storing user data and storing ECC codes, with the controller intelligently managing both functions. This universal approach eliminates the need for dedicated separate memory arrays for error correction, reducing overall device complexity.
Data Source
AI summary
An integrated circuit includes a memory having an address space and a memory controller coupled to the memory for accessing the address space in response to received memory accesses. The memory controller further accesses a plurality of data elements in a first portion of the address space, and reliability data corresponding to the plurality of data elements in a second portion of the address space.