Memory Controller Staggered Request Signal Output
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Solution Overview
Problem
In modern memory systems, the varying capacitive loading of command/address signal lines and control signal lines leads to request skew, which consumes a larger portion of the signal eye and limits maximum request signaling rates as signaling rates increase, due to differences in propagation times.
Innovation Solution
A memory controller with timing circuitry is implemented to provide programmable phase offsets between the output times of control signals and command/address signals, mitigating signal propagation time differences by establishing separate programmable phase offsets for control and command/address signals, allowing for staggered output times to compensate for loading variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If command/address signals and control signals are transmitted simultaneously on signal lines with different capacitive loading, then the memory system can operate at higher signaling rates, but request skew increases and consumes a larger portion of the signal eye
Solution Approach 1:
The patent applies preliminary action by outputting control signals earlier than command/address signals. A timing circuit generates a timing signal that triggers control signal output before the main clock signal triggers command/address signal output. This pre-positioning of control signals compensates for their faster propagation speed on lightly-loaded lines, ensuring both signal types arrive at memory devices simultaneously, thereby eliminating request skew while maintaining high signaling rates
Solution Approach 2:
The patent changes the temporal parameter of signal output by introducing a programmable phase offset between control signals and command/address signals. The timing circuit allows adjustment of the phase relationship between the timing signal (controlling control signals) and clock signal (controlling command/address signals), enabling dynamic optimization of signal arrival alignment based on actual loading conditions and propagation characteristics
2Productivity
If dedicated control signal lines are provided for each memory rank while command/address lines are shared, then control signals can be transmitted in parallel to multiple ranks, but the capacitive loading difference causes skew between control and command/address signals
Solution Approach 1:
The patent applies local quality by providing separate, dedicated control signal lines for each memory rank while using shared command/address lines. This allows control signals to be transmitted in parallel to multiple ranks simultaneously, maximizing productivity. The timing circuit compensates for the different loading conditions on dedicated versus shared lines by introducing appropriate phase offsets, ensuring synchronization is maintained despite the different signal path characteristics
Data Source
AI summary
A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.