Memory Controller Staggering Peak Current Operations
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Solution Overview
Problem
The challenge in NAND type flash memory systems is the increased operation current when multiple memory chips are operated simultaneously, leading to overlapping peak currents and high power consumption, which is difficult to manage due to varying clock cycles and cell characteristics.
Innovation Solution
A memory system comprising multiple nonvolatile semiconductor memory chips and a controller that controls the operations of these chips by staggering the timing of peak current-generating operations through a resume command mechanism, allowing each chip to enter a suspend state after peak current periods and resume only when necessary, thereby preventing peak current overlaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple NAND type flash memory chips are operated simultaneously to improve write performance, then the write speed of the memory system is improved, but the operation current increases and peak currents overlap causing high power consumption
Solution Approach 1:
The memory chips are placed in a suspend state before peak current operations to prevent current overlap. The controller coordinates the resumption of operations so that peak current periods do not coincide, thereby preliminarily avoiding the harmful effect of current overlap while maintaining parallel operation capability
Solution Approach 2:
The memory chips dynamically switch between suspend and active states based on operation phase. During peak current periods, chips enter suspend state, and during low current periods, chips remain active or resume operations, creating a dynamic power management scheme that adapts to instantaneous current requirements
2Productivity
If multiple memory chips are operated at the same time, then data processing capacity increases, but peak current overlap becomes difficult to manage due to varying clock cycles and cell characteristics
Solution Approach 1:
The controller monitors the operation states of multiple memory chips and provides feedback control by issuing suspend and resume commands. This feedback mechanism allows the controller to coordinate peak current timing across chips with varying clock cycles and characteristics, simplifying current management through centralized control
Solution Approach 2:
The controller acts as an intermediary that mediates between multiple memory chips with different operating characteristics. It standardizes the coordination of peak current operations by managing the suspend/resume states, thereby simplifying the overall system current management despite individual chip variations
Data Source
AI summary
According to one embodiment, a memory system includes a first nonvolatile semiconductor memory, a second nonvolatile semiconductor memory and a controller. The first memory has memory cells and executes a first operation that is at least one of write, read, and erase operations with respect to the memory cells. The first operation includes a first sub-operation and a second-sub operation that consume a current which is equal to or higher than a predetermined current. The second memory has memory cells and executes a second operation that is at least one of write, read, and erase operations with respect to the memory cells. The second operation includes a third sub-operation and a fourth sub-operation that consume a current which is equal to or higher than the predetermined current. The controller controls the first operation and the second operation of the first memory and the second memory.