Memory Controller Status Arbiter Logic Complexity

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing methods for accessing status information from memory devices are inefficient due to increased logic complexity, higher latency, and excessive data paths, which hinder the effective transfer of status information from controllers to hosts in electronic systems.

Innovation Solution

The implementation of a status channel with a status arbiter that includes a status intermediary, which reduces logic components, employs time-division multiplexing to minimize data paths, and continuously polls status request signals to lower latency, allowing for efficient routing and reduced latency in transferring status information.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional methods for accessing status information from memory devices are used, then status information can be transferred from controllers to hosts, but the logic complexity increases and latency is higher

Engineering Contradiction:
Improvestatus information transferVSAvoidlogic complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a status intermediary component that acts as a mediator between the memory controller and the host. This intermediary receives status information from the controller, manages the status data, and interfaces with the host, thereby simplifying the overall logic complexity while maintaining reliable status information transfer.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If traditional status information access methods are used, then status information can be retrieved, but the latency is increased

Engineering Contradiction:
Improvestatus information accessVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The status intermediary continuously monitors and pre-fetches status information from the memory controller before the host actually requests it. By preparing status data in advance and maintaining a ready state, the system reduces the time required to deliver status information when the host needs it, thereby lowering latency while ensuring reliable access.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If existing status information transfer methods are used, then status data can be communicated from controllers to hosts, but excessive data paths are created

Engineering Contradiction:
Improvestatus information communicationVSAvoiddata paths
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent consolidates multiple status information transfer paths into a single unified interface through the status intermediary. Instead of having separate data paths from each memory controller to each host, the intermediary merges these paths, receiving status information from controllers and presenting a unified interface to the host, thereby reducing the number of data paths and associated complexity while maintaining reliable communication.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10725952B2Accessing status information
Publication Date: 2020.07.28 MICRON TECHNOLOGY INC
  • US10725952B2 patent drawing
  • US10725952B2 patent drawing
  • US10725952B2 patent drawing

AI summary

The present disclosure includes apparatuses and methods related to accessing status information. One example apparatus comprises a host and a memory device coupled to the host. The memory device includes a controller configured to provide, to a status arbiter, a status signal indicating whether a status register of the controller contains generated status information. Responsive to the status signal indicating that the status register contains the generated status information, the controller can also provide the status information from the controller to the status arbiter via a status intermediary.