Memory Controller Adaptive Status Check Timing
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Solution Overview
Problem
Existing memory systems experience long idle times on the system bus during program operations due to inefficient status check timing, leading to performance degradation and unnecessary resource wastage.
Innovation Solution
Implementing an adaptive status check timing control method that groups memory devices based on program times, allowing for varied delay times for different word lines or memory blocks to optimize status check operations and prevent repetitive checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed delay time is used for status check operations, then the control logic is simple, but long idle times occur on the system bus during program operations
Solution Approach 1:
The patent divides the memory device into multiple memory blocks, each with its own program time characteristics. The status check operation is segmented to occur at different delay times for different memory blocks, allowing the system to check status efficiently without causing long idle times on the system bus.
Solution Approach 2:
The patent implements dynamic delay time adjustment based on program operation characteristics. The memory controller adjusts the delay time for status check operations according to the specific program time of each memory block, transforming the fixed delay approach into a dynamic one that adapts to actual program completion times.
2Measurement precision
If status check operations are performed frequently, then program completion can be detected accurately, but system performance degrades due to unnecessary resource wastage
Solution Approach 1:
The patent applies partial action by performing status check operations only at necessary delay times for each memory block. Instead of frequent checks for all blocks, the system checks status at optimized delay times, reducing unnecessary resource wastage while maintaining accurate program completion detection.
Solution Approach 2:
The patent changes the delay time parameter for status check operations based on program operation characteristics. By adjusting this parameter dynamically, the system achieves accurate program completion detection without the need for frequent status checks, thereby maintaining high system performance.
3Device complexity
If uniform status check timing is applied to all memory blocks, then the control mechanism is simple, but efficiency is reduced due to repetitive checks
Solution Approach 1:
The patent applies local quality by setting different delay times for status check operations in different memory blocks. Each memory block receives a customized delay time based on its program time characteristics, eliminating repetitive checks and improving overall memory system efficiency while maintaining reasonable control mechanism complexity.
Data Source
AI summary
A memory system, a memory device, a memory controller and an operating method thereof. By issuing a first status check signal when a first delay time elapses since a first point in time at which a program operation for first memory cells corresponding to a first word line is started and by issuing a second status check signal when a second delay time different from the first delay time elapses since a second point in time at which a program operation for second memory cells corresponding to a second word line is started, it is possible to efficiently perform a status check operation related with a program operation of data.