Memory Controller Status Check via Shared I/O Lines

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Solution Overview

Problem

Current memory systems face challenges in reducing channel size and increasing operation speed, particularly in determining the status of multiple memory chips efficiently through input/output lines.

Innovation Solution

A memory system design that includes memory chips configured to output ready/busy signals in response to status check commands, with a memory controller transmitting these commands through input/output lines to determine the operation status of memory chips, allowing for simultaneous status checks across multiple chips or grouped memory units.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple memory chips are coupled to a channel, then data storage capacity increases, but channel size and complexity increase

Engineering Contradiction:

Improvedata storage capacityVSAvoidchannel size

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent merges the status check functionality into the existing input/output lines that are already used for data transmission. Instead of adding separate dedicated status lines for each memory chip, the system uses the shared I/O lines to carry both data and status information, thereby reducing channel complexity while maintaining the ability to monitor multiple chips.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The input/output lines are designed to serve multiple functions: they transmit data between the memory controller and memory chips, and simultaneously carry ready/busy status signals. This multi-functionality eliminates the need for separate status lines, reducing the overall channel size while supporting multiple memory chips.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If status check commands are transmitted to multiple memory chips, then operation status determination improves, but operation time increases

Engineering Contradiction:

Improveoperation status determinationVSAvoidstatus check operation time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent implements continuous status monitoring by having memory chips continuously drive their ready/busy signals onto the shared I/O lines. This allows the memory controller to continuously monitor the status of multiple chips without needing to initiate separate polling operations, thereby reducing status check time while maintaining reliable status determination.

Inventive Principle:

Principle #20Continuity of useful action

Solution Approach 2:

Memory chips automatically drive their status signals onto the shared I/O lines without requiring active polling from the controller. The chips self-serve by continuously making their status information available on the communication lines, allowing the controller to passively monitor multiple chips simultaneously and determine their operation status efficiently.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS10191692B2Memory device and method of operating the same

Publication Date: 2019.01.29 SK HYNIX INC

AI summary

Disclosed herein is a memory system including: a plurality of memory chips coupled to a plurality of input/output lines included in a channel and output ready/busy signals to the input/output lines in response to a status check command; and a memory controller configured to transmit the status check command to the memory chips through the channel and simultaneously determine an operation status of the memory chips depending on the ready/busy signals received through the input/output lines.