Memory Controller Single-Cycle Storage Initialization
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Solution Overview
Problem
The initialisation of memory in computing systems is becoming increasingly time- and power-consuming as memory capacity and application demand grow, with existing methods requiring multiple clock cycles to initialise large portions of memory, leading to processing delays and high write currents.
Innovation Solution
A system and method for initialising a portion of storage over a single clock cycle using a memory controller that generates initialisation signals to initialise a plurality of bitcells simultaneously, including an initialise address signal, initialise range signal, and initialise data signal, allowing multiple bitcells to be initialised in a single clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory initialisation is performed using conventional methods (multiple clock cycles), then security requirements are met (memory is initialised), but processing time increases and system performance deteriorates
Solution Approach 1:
The memory array is divided into multiple banks, and the initialisation operation is segmented across these banks. The memory controller can initialise multiple banks simultaneously using parallel write operations, thereby reducing the total initialisation time while maintaining security requirements.
Solution Approach 2:
The system determines whether initialisation is actually needed before performing it. By checking if the memory contains sensitive data or will be accessed by untrusted processes, the system可以避免 unnecessary initialisation operations, thus reducing time loss while maintaining security when required.
2Reliability
If memory initialisation is performed to secure data, then security is improved, but power consumption increases due to multiple write operations
Solution Approach 1:
Instead of initialising the entire memory array, the system performs partial initialisation only on the specific banks or regions that contain or will contain sensitive data. This reduces the total number of write operations and associated power consumption while maintaining adequate security for the sensitive portions.
Solution Approach 2:
The system performs a preliminary assessment to identify which memory regions require initialisation. By using address range information and process trust levels, it determines the minimum necessary initialisation scope, avoiding excessive write operations and reducing power consumption.
3Quantity of substance
If memory capacity is increased to meet application demand, then storage capability is improved, but initialisation time and complexity increase
Solution Approach 1:
The large-capacity memory is organised into multiple manageable banks. This segmentation allows the memory controller to initialise only the necessary banks in parallel, rather than sequentially initialising the entire large capacity memory, thus reducing initialisation time despite increased total capacity.
Solution Approach 2:
The memory controller is designed to handle multiple functions including initialisation, data access, and security management. It can perform initialisation operations on multiple banks simultaneously using unified control logic, improving efficiency as memory capacity and bank count increase.
4Reliability
If comprehensive memory initialisation is performed, then security against data leakage is improved, but processing speed deteriorates due to time-consuming operations
Solution Approach 1:
The system performs preliminary checks to determine whether memory initialisation is actually required based on the trust level of the accessing process and the sensitivity of the data. This avoids unnecessary initialisation operations that would slow down processing, while still maintaining security when needed.
Solution Approach 2:
The system performs partial initialisation only on memory regions containing or intended for sensitive data, rather than initialising the entire memory space. This maintains security against data leakage for critical regions while minimising the impact on overall processing speed.
Data Source
AI summary
There is provided a system comprising: a storage device having a storage portion comprising a plurality of bitcells coupled to respective first signal lines and second signal lines and control logic to alter a memory state of the plurality of bitcells via the first signal lines and second signal lines; a memory controller coupled to the storage device to transmit one or more initialisation signals to the storage device; wherein the storage device is to initialise the storage portion over a clock cycle in response to the one or more initialisation signals.