Memory Controller Buffering for Straddling Cluster Data Transfer
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Solution Overview
Problem
Current memory systems face challenges in maximizing data transfer rates from memory chips to controllers due to constraints in handling straddling clusters, where data is split across two planes, requiring sequential operations that limit parallel processing and increase data transfer time.
Innovation Solution
The implementation of a memory system with a controller that uses a waiting buffer group and random buffer to manage data transfer by buffering data from one plane and combining fragments from both planes, allowing for parallel operation and reducing the need for timing adjustments between data-out operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is read sequentially from memory chip planes, then data transfer can be performed, but data transfer rate is limited due to sequential operations on straddling clusters
Solution Approach 1:
The patent divides the memory chip into multiple planes (first plane and second plane) that can be operated independently. Each plane has its own data latch and buffer, allowing parallel data reading operations. This segmentation enables simultaneous data retrieval from different planes, resolving the sequential operation bottleneck and improving data transfer rate.
Solution Approach 2:
The patent introduces a waiting buffer group that operates in a different temporal dimension, buffering data from one plane while another plane is being read. This allows the system to overlap data transfer operations across planes, effectively adding a time dimension to the parallel processing and reducing total data transfer time.
2Productivity
If planes are operated in parallel, then data transfer rate increases, but timing adjustments between data-out operations become more complex
Solution Approach 1:
The waiting buffer group acts as an intermediary between the parallel plane operations and the controller. It receives data from one plane and holds it while another plane's data is being transferred, eliminating the need for complex timing adjustments. The buffer group mediates the data flow, allowing planes to operate independently without synchronizing their data-out operations.
Solution Approach 2:
The waiting buffer group performs preliminary buffering of data from one plane before it is needed by the controller. This advance action allows the system to prepare data in advance, eliminating timing constraints and allowing planes to operate in parallel without complex synchronization.
3Productivity
If straddling clusters are handled with sequential operations, then data can be transferred, but processing efficiency decreases
Solution Approach 1:
The patent segments the memory chip into multiple independently operable planes, allowing straddling clusters to be handled by reading from different planes in parallel. This segmentation enables simultaneous data retrieval operations, improving processing efficiency and reducing the time required to handle straddling clusters.
Solution Approach 2:
The waiting buffer group maintains continuous data transfer by buffering data from one plane while another plane is being read. This ensures that data transfer operations are continuous and overlapping, eliminating idle time and improving overall processing efficiency for straddling cluster handling.
Data Source
AI summary
A memory system includes a controller that: in a case where first data being a read target is stored across a first storage area of a first plane and a second storage area of a second plane, causes a memory chip to perform sensing to second data including a first fragment of the first data; causes the memory chip to perform sensing to third data including a second fragment of the first data stored in the second storage area; stores the second data in a first buffer; stores the third data in a second buffer; reads the first and second fragments from the first and second buffers respectively; combines the fragments to generate fourth data; and inputs the fourth data to an error correction circuit.