Memory Controllers Using Authenticated Stream Ciphers for Concurrent Access

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Solution Overview

Problem

Existing memory architectures face complexity and inefficiency in securing non-volatile dual in-line memory modules (NVDIMMs) due to cumbersome cryptographic methods, which hinder concurrent processing of memory access requests, address translation, and error correction.

Innovation Solution

A memory controller utilizes an authenticated stream cipher to generate an access code concurrently with address translation and error correction, enhancing processing speed by parallel execution of these tasks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional block ciphers are used for securing memory access, then data authentication is achieved, but processing speed decreases and concurrent processing becomes difficult

Engineering Contradiction:
Improvedata authenticationVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent changes the cryptographic parameter from block cipher to stream cipher, which fundamentally alters the processing characteristics. Stream ciphers process data in a continuous stream rather than fixed blocks, enabling concurrent execution with memory access operations and significantly improving processing speed while maintaining authentication security.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the traditional sequential mechanical processing of block ciphers with a stream-based approach that allows parallel execution. By substituting the block-oriented cryptographic mechanism with a stream-oriented one, the system achieves concurrent processing of encryption, address translation, and error correction operations.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Device complexity

If sequential processing is used for address translation, error correction, and encryption, then processing complexity is reduced, but overall processing time increases

Engineering Contradiction:
Improveprocessing complexityVSAvoidprocessing time
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent implements preliminary action by preparing cryptographic keys and initialization vectors in advance, and by structuring the stream cipher to process data as it becomes available during memory operations. This allows the encryption process to run concurrently with address translation and error correction without requiring complex coordination, reducing overall processing time while maintaining manageable complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The stream cipher provides continuous processing capability, allowing encryption operations to proceed continuously alongside address translation and error correction. This continuity eliminates the sequential bottlenecks present in block cipher approaches, reducing total processing time without significantly increasing device complexity.

Inventive Principle:
Principle #20Continuity of useful action

3Productivity

If concurrent processing is implemented for multiple memory operations, then processing speed improves, but device complexity increases

Engineering Contradiction:
Improveprocessing speedVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary approach by using a memory controller that coordinates the concurrent operations. The memory controller acts as a mediator between the stream cipher encryption, address translation, and error correction functions, managing their parallel execution and data flow. This intermediary structure enables concurrent processing to improve speed while keeping the overall device complexity manageable through centralized coordination.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250335107A1Memory systems and devices including examples of accessing memory and generating access codes using an authenticated stream cipher
Publication Date: 2025.10.30 MICRON TECHNOLOGY INC
  • US20250335107A1 patent drawing
  • US20250335107A1 patent drawing
  • US20250335107A1 patent drawing

AI summary

Examples of systems and methods described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and/or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.