Nonvolatile Memory Controller Block Management for Stream Data
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Solution Overview
Problem
Data writing in semiconductor memory cards slows down significantly when updating large volumes of content data, as existing memory controllers are unaware of the need to rewrite entire blocks, leading to inefficient data organization and slowed writing speeds.
Innovation Solution
A nonvolatile memory device with a memory controller that includes an interface unit, address management unit, and read/write control unit, which determines a new block for writing data based on received commands, reducing the need for frequent block rewrites by managing data writing through a first and second write range, and optionally abandoning or erasing blocks to ensure secure new block determination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the memory controller uses traditional block management methods, then data writing can proceed with simple block allocation, but data writing speed slows down significantly when blocks need to be rewritten
Solution Approach 1:
The memory controller receives a stream data write command that identifies a write range spanning multiple blocks, and proactively determines and prepares new blocks for writing before the actual data writing occurs. This preliminary block determination prevents the need for time-consuming block rewriting operations during data writing, thereby maintaining high writing speed.
Solution Approach 2:
The write range is divided into multiple individual blocks, and the memory controller determines new blocks for each segment independently. This segmentation allows parallel processing of block allocation and prevents conflicts that would arise from managing the entire write range as a single unit, thus improving overall writing efficiency.
2Productivity
If the memory controller determines new blocks after data writing, then block allocation remains simple, but data writing speed is significantly reduced due to frequent block rewrites
Solution Approach 1:
The memory controller performs block determination in advance by receiving the stream data write command with write range information, identifying which blocks will be affected, and preparing new blocks before actual writing. This preliminary action improves productivity by avoiding mid-write block rewrites, while the complexity is managed through automated controller logic.
Solution Approach 2:
The memory controller uses feedback from the write command (which includes write range identification) to dynamically determine and allocate appropriate new blocks. This feedback mechanism allows the controller to adapt block allocation to actual writing needs without requiring complex pre-planning or manual intervention.
3Adaptability or versatility
If the memory controller manages blocks individually without stream data awareness, then block allocation is straightforward, but it cannot anticipate when entire blocks need to be rewritten
Solution Approach 1:
The memory controller enhances adaptability by receiving stream data write commands that provide advance notice of writing operations. This allows the controller to anticipate which blocks will be completely rewritten and prepare new blocks in advance, adapting block management to stream data patterns without significantly increasing complexity through automated determination logic.
Solution Approach 2:
The memory controller autonomously determines new blocks for writing based on the write range information provided in the command, without requiring external intervention or complex coordination with the host device. This self-service capability improves adaptability to different writing scenarios while keeping the block management mechanism relatively simple through automated decision-making.
Data Source
AI summary
The nonvolatile memory device prevents data writing from temporarily slowing down significantly in the middle of writing data to a block when an access device writes all the data in the block in units of a smaller size than the block. The nonvolatile memory device comprises a memory controller including an interface unit configured to receive a first command that identifies a first write range for writing data, and a second command that identifies a second write range that is a part of the first write range and orders to write data to the second write range, an address management unit configured to determine, before data is written into a nonvolatile memory, a new block for writing data to the first write range based on the first command, and a read/write control unit configured to write data to the new block in response to the second command.