Memory Controller ppDLL and ppDCC for Strobe Alignment
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Solution Overview
Problem
Flash memory devices experience signal distortion during operation, leading to failed data transmission and reception, which affects the normal functioning of the controller and memory device.
Innovation Solution
The controller performs per-pin delay locked loop (ppDLL) and per-pin duty cycle correction (ppDCC) operations on data signals based on the rising and falling edges of the data strobe signal to align the edges of the data signals with the strobe signal, thereby compensating for signal distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If per-pin delay locked loop (ppDLL) and per-pin duty cycle correction (ppDCC) operations are performed on each data signal, then signal distortion is compensated and data transmission reliability is improved, but device complexity and processing time increase
Solution Approach 1:
The controller performs ppDLL and ppDCC operations independently on each data signal pin (DQ0-DQ7) rather than as a group. Each pin undergoes separate delay adjustment and duty cycle correction, allowing targeted compensation for signal distortion specific to each pin's electrical characteristics and trace length, thereby improving overall reliability while managing complexity through modular processing
Solution Approach 2:
The ppDLL and ppDCC operations are performed during a training phase before normal data transmission begins. This preliminary calibration establishes optimal delay and duty cycle parameters for each pin in advance, so that during actual operation, the controller can use pre-determined settings without real-time adjustments, reducing processing time and operational complexity
2Productivity
If ppDLL and ppDCC operations are performed simultaneously on multiple data signals, then data transmission speed is improved, but signal distortion compensation precision may be reduced
Solution Approach 1:
The simultaneous operation is achieved by independently processing each data pin through separate ppDLL and ppDCC circuits operating in parallel. Each pin's delay and duty cycle are adjusted independently without interfering with other pins, maintaining precision while achieving speed through parallel execution of the same correction algorithm across multiple channels
Solution Approach 2:
A training mode is introduced as an intermediary state between calibration and normal operation. During training mode, the controller sequentially tests and optimizes each pin's parameters using test patterns, storing the optimal settings in registers. This intermediary calibration phase ensures precision is established before high-speed parallel operation begins
Data Source
AI summary
Disclosed is an operation method of a controller which communicates with a plurality of memory devices. The method includes receiving a first reception signal, a second reception signal, and a data strobe signal, respectively, generating a first delay signal by performing first and second per-pin delay locked loop (ppDLL) operations on the first and second reception signals based on a rising edge of the data strobe signal, respectively, and generating first and second correction signals by performing first and second per-pin duty cycle correction (ppDCC) operations on the first and second delay signals based on a falling edge of the data strobe signal, respectively. Rising edges of the first and second correction signals are aligned with the rising edge of the data strobe signal, and first and second falling edges of the first correction signals are aligned with the falling edge of the data strobe signal.