Memory Controller Data Strobe Calibration via Auto Refresh
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Solution Overview
Problem
Conventional DDR memory controllers face challenges in accurately compensating data strobe skew due to variable latencies induced by temperature, circuit mismatch, and wire length, making precise calibration difficult and inefficient, especially during auto refresh cycles where idleness is wasteful.
Innovation Solution
A memory controller with a DQ path, DQS path, delay element, flip flop, and adjustment unit that uses a calibration method involving a calibration pattern to determine the optimal latency difference between data and data strobe signals, allowing for periodic adjustments to maintain accurate sampling and reduce latency variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a delay element and delay calibration circuit are used to compensate for latency differences between DQ and DQS paths, then data sampling accuracy is improved, but the system complexity increases and accurate compensation becomes difficult due to variable latencies from temperature, circuit mismatch, and wire length
Solution Approach 1:
The system uses the idle auto refresh period to automatically perform calibration without external intervention. The memory controller autonomously adjusts the delay element using calibration patterns generated during the refresh cycle, eliminating the need for complex external calibration equipment while maintaining sampling accuracy
Solution Approach 2:
The calibration circuit uses feedback from sampled calibration patterns to iteratively adjust the delay element. By comparing sampled data with expected calibration patterns, the system automatically tunes the delay to compensate for latency variations, achieving accurate compensation through closed-loop control rather than open-loop complexity
2Reliability
If conventional auto refresh cycles are used, then memory refresh function is performed, but idle periods are wasted without data transmission
Solution Approach 1:
The system eliminates idle periods by continuously performing useful calibration actions during the auto refresh cycle. Instead of leaving DQ and DQS paths idle during refresh, the system transmits calibration patterns and performs delay calibration, ensuring that every clock cycle serves a productive purpose while maintaining memory refresh reliability
Solution Approach 2:
The auto refresh cycle serves dual functions: maintaining memory data integrity through refresh and performing delay calibration for optimal sampling. By making the refresh cycle multi-functional, the system eliminates wasted idle time while ensuring both memory reliability and calibration accuracy are achieved simultaneously
3Ease of manufacture
If latency compensation is performed using fixed delay values, then circuit design is simplified, but accurate compensation is difficult to achieve due to temperature variations, circuit mismatch, and wire length differences
Solution Approach 1:
The system transitions from fixed delay values to dynamic, adjustable delay through the delay element controlled by the calibration circuit. The delay can be programmatically adjusted based on measured conditions, allowing the circuit to adapt to temperature variations and mismatches while maintaining relatively simple base circuitry that can be configured through control signals
Data Source
AI summary
A memory controller comprises a DQ path, a DQS path, a delay element, a flip flop, and an adjustment unit. The DQ path receives and passes a data signal, and outputs a delayed data signal. The DQS path receives and passes a data strobe signal. The delay element is coupled to the DQS path, receiving the data strobe signal to generate a compensated data strobe signal having a calibrated latency. The calibrated latency is determined by an adjustment signal. The flip flop is coupled to the data signal path and the delay element, sampling the delayed data signal by the compensated data strobe signal to generate an output data. The adjustment unit generates the adjustment signal according to the output data. The adjustment unit performs a calibration to adjust the adjustment signal, thus the calibrated latency is adjusted.